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<p>High-speed multimedia applications have increased the need for fault-tolerant circuits that compromise accuracy while increasing performance. Approximation computation has emerged as an attractive approach to minimize power consumption. Improving the performance of multipliers is essential because they are key components in various applications, including image processing and advanced learning algorithms. However, striking a balance between accuracy and power consumption is one of the main challenges of these circuits. The design of approximation compressors, as a key building block in the structure of multiplication circuits, requires a trade-off between accuracy, circuit complexity, power consumption, and error rate. This study presents novel 8 × 8 and 16 × 16 Dadda multiplier architectures, which are designed with novel 4:2 and 7:2 approximation compressor circuit structures using current-state logic, level-detection inverters, and logic gates with a minimum transistor count under the 32&#xa0;nm CNTFET framework. The proposed architectures and techniques are presented on the circuit to consume very low power and dimensions and are most suitable for approximate image processing. Using HSPICE simulations and Matlab evaluations, the designs show significant improvements in power, latency, and transistor count while meeting acceptable image quality standards. These multipliers have been investigated in image multiplication, edge detection, and noise filtering applications in the field of image processing. These studies show that the proposed architecture for designing multipliers and compressors for scalable and energy-efficient approximate calculations provides excellent performance compared to the exact multiplication model and achieves good results for fault-tolerant applications.</p>

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CNTFET-based low-power approximate compressors with current-mode and pass-transistor logic for image processing

  • 期刊论文

  • 发表日期：

    2026年6月2日

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  • Pegah Foroutan,
  • Keivan Navi

摘要

High-speed multimedia applications have increased the need for fault-tolerant circuits that compromise accuracy while increasing performance. Approximation computation has emerged as an attractive approach to minimize power consumption. Improving the performance of multipliers is essential because they are key components in various applications, including image processing and advanced learning algorithms. However, striking a balance between accuracy and power consumption is one of the main challenges of these circuits. The design of approximation compressors, as a key building block in the structure of multiplication circuits, requires a trade-off between accuracy, circuit complexity, power consumption, and error rate. This study presents novel 8 × 8 and 16 × 16 Dadda multiplier architectures, which are designed with novel 4:2 and 7:2 approximation compressor circuit structures using current-state logic, level-detection inverters, and logic gates with a minimum transistor count under the 32 nm CNTFET framework. The proposed architectures and techniques are presented on the circuit to consume very low power and dimensions and are most suitable for approximate image processing. Using HSPICE simulations and Matlab evaluations, the designs show significant improvements in power, latency, and transistor count while meeting acceptable image quality standards. These multipliers have been investigated in image multiplication, edge detection, and noise filtering applications in the field of image processing. These studies show that the proposed architecture for designing multipliers and compressors for scalable and energy-efficient approximate calculations provides excellent performance compared to the exact multiplication model and achieves good results for fault-tolerant applications.