<p>Versatile Video Coding (VVC) offers a compression efficiency improvement of 50% and 75% compared to its predecessors, High Efficiency Video Coding (HEVC) and Advanced Video Coding (AVC), respectively. The VVC encoder software (VVENC), while highly efficient, remains exceedingly complex and operates at speeds that are not conducive to real-time encoding. Despite various speed-optimized versions being released since its standardization in 2020, the complexity remains substantial. This complexity primarily arises from the multiple transform selection (MTS) feature, which involves three transform types (DCT-II, DCT-VIII, and DST-VII) and various rectangular transform sizes ranging from <InlineEquation ID="IEq1"> <InlineMediaObject> <ImageObject Color="BlackWhite" FileRef="10586_2024_5020_Article_IEq1.gif" Format="GIF" Height="14" Rendition="HTML" Resolution="72" Type="Linedraw" Width="39" /> </InlineMediaObject> <EquationSource Format="TEX">$2\times 2$</EquationSource> <EquationSource Format="MATHML"><math> <mrow> <mn>2</mn> <mo>×</mo> <mn>2</mn> </mrow> </math></EquationSource> </InlineEquation> to <InlineEquation ID="IEq2"> <InlineMediaObject> <ImageObject Color="BlackWhite" FileRef="10586_2024_5020_Article_IEq2.gif" Format="GIF" Height="14" Rendition="HTML" Resolution="72" Type="Linedraw" Width="54" /> </InlineMediaObject> <EquationSource Format="TEX">$64\times 64$</EquationSource> <EquationSource Format="MATHML"><math> <mrow> <mn>64</mn> <mo>×</mo> <mn>64</mn> </mrow> </math></EquationSource> </InlineEquation>. In this research paper, we propose a unified transform architecture (UTA) that encompasses all transform types and sizes specified in VVENC. It supports both forward as well as inverse transform. The proposed architecture features a reusable one-dimensional transform system, consisting of two 32-point transform subsystems to perform the two-dimensional transform. This architecture can process up to 64 samples in parallel, achieving a high throughput. The architecture is implemented in VHDL and implemented on an Intel Arria 10 FPGA board, achieving a throughput of up to 332 fps at <InlineEquation ID="IEq3"> <InlineMediaObject> <ImageObject Color="BlackWhite" FileRef="10586_2024_5020_Article_IEq3.gif" Format="GIF" Height="14" Rendition="HTML" Resolution="72" Type="Linedraw" Width="86" /> </InlineMediaObject> <EquationSource Format="TEX">$3840\times 2160$</EquationSource> <EquationSource Format="MATHML"><math> <mrow> <mn>3840</mn> <mo>×</mo> <mn>2160</mn> </mrow> </math></EquationSource> </InlineEquation> resolution with <InlineEquation ID="IEq4"> <InlineMediaObject> <ImageObject Color="BlackWhite" FileRef="10586_2024_5020_Article_IEq2.gif" Format="GIF" Height="14" Rendition="HTML" Resolution="72" Type="Linedraw" Width="54" /> </InlineMediaObject> <EquationSource Format="TEX">$64\times 64$</EquationSource> <EquationSource Format="MATHML"><math> <mrow> <mn>64</mn> <mo>×</mo> <mn>64</mn> </mrow> </math></EquationSource> </InlineEquation> transform sizes. This makes the architecture a viable candidate for use as a co-processor with the VVENC software.</p>

A high-throughput unified transform architecture for Versatile Video Coding

期刊论文
发表日期：

2025年4月28日

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Mohd Rafi Lone

摘要

Versatile Video Coding (VVC) offers a compression efficiency improvement of 50% and 75% compared to its predecessors, High Efficiency Video Coding (HEVC) and Advanced Video Coding (AVC), respectively. The VVC encoder software (VVENC), while highly efficient, remains exceedingly complex and operates at speeds that are not conducive to real-time encoding. Despite various speed-optimized versions being released since its standardization in 2020, the complexity remains substantial. This complexity primarily arises from the multiple transform selection (MTS) feature, which involves three transform types (DCT-II, DCT-VIII, and DST-VII) and various rectangular transform sizes ranging from $2\times 2$ $2 \times 2$ to $64\times 64$ $64 \times 64$ . In this research paper, we propose a unified transform architecture (UTA) that encompasses all transform types and sizes specified in VVENC. It supports both forward as well as inverse transform. The proposed architecture features a reusable one-dimensional transform system, consisting of two 32-point transform subsystems to perform the two-dimensional transform. This architecture can process up to 64 samples in parallel, achieving a high throughput. The architecture is implemented in VHDL and implemented on an Intel Arria 10 FPGA board, achieving a throughput of up to 332 fps at $3840\times 2160$ $3840 \times 2160$ resolution with $64\times 64$ $64 \times 64$ transform sizes. This makes the architecture a viable candidate for use as a co-processor with the VVENC software.