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<p>In mixed-signal integrated circuit design, comparators are essential, especially for low-power, high-speed applications such as data converters, communication systems, and portable devices. Conventional comparator designs often struggle to balance speed and power efficiency. This paper proposes a low-power, high-speed modified strongARM latch circuit topology with an offset correction. The proposed design performance is compared with open-loop, preamplifier latch-based, and strongARM latch comparators. The proposed design incorporates innovative architectural modifications to enhance speed, power efficiency, and offset. The proposed comparator achieves significant delay reductions of 61%, 55%, and 47% compared to the open-loop, preamplifier latch-based, and strongARM latch comparators, respectively. Furthermore, the proposed design achieves a 30.7% reduction in dynamic power dissipation compared to the strongARM design. PVT analysis was performed by evaluating the design across standard corners (TT, FF and SS) and under a 5% drop in supply voltage (1.0&#xa0;V to 0.95&#xa0;V). The offset correction mechanism of the proposed comparator significantly increases the number of successful output samples, which can be observed through Monte Carlo simulation using Synopsys Custom Compiler at a 32&#xa0;nm technology node.</p>

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A 4.9 GS/s strongarm latch comparator topology with offset correction in 32-nm

  • 期刊论文

  • 发表日期：

    2026年7月11日

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  • Chokkakula Ganesh,
  • A. Murali,
  • B. Vamsy Krishna,
  • T. Ananda Babu,
  • Girraj Sharma,
  • Asisa Kumar Panigrahy,
  • M. Durga Prakash

摘要

In mixed-signal integrated circuit design, comparators are essential, especially for low-power, high-speed applications such as data converters, communication systems, and portable devices. Conventional comparator designs often struggle to balance speed and power efficiency. This paper proposes a low-power, high-speed modified strongARM latch circuit topology with an offset correction. The proposed design performance is compared with open-loop, preamplifier latch-based, and strongARM latch comparators. The proposed design incorporates innovative architectural modifications to enhance speed, power efficiency, and offset. The proposed comparator achieves significant delay reductions of 61%, 55%, and 47% compared to the open-loop, preamplifier latch-based, and strongARM latch comparators, respectively. Furthermore, the proposed design achieves a 30.7% reduction in dynamic power dissipation compared to the strongARM design. PVT analysis was performed by evaluating the design across standard corners (TT, FF and SS) and under a 5% drop in supply voltage (1.0 V to 0.95 V). The offset correction mechanism of the proposed comparator significantly increases the number of successful output samples, which can be observed through Monte Carlo simulation using Synopsys Custom Compiler at a 32 nm technology node.