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<p>Orthogonal Time Frequency Space (OTFS) modulation has gained attention as a reliable wireless communication technique, especially under high-mobility and time-varying channel conditions. However, conventional OTFS transceiver designs face significant challenges in terms of hardware complexity, low throughput, and inefficient execution in multi-path fading environments. To overcome these limitations, this paper introduces an OTFS Transceiver with Low-Complexity VLSI Architecture in A Fully Parallel and Pipelined Hardware Architecture in Cosine-Krawtchouk Point-wise Discrete Activations Tchebichef Steerable Lyrebird Convolutional Transforms Networks (CosKPWD-ATSL-CTN). The suggested CosKPWD-ATSL-CTN framework combines Point-wise Activations and Steerable Convolutional Networks (PWASCN) with Discrete Cosine-Krawtchouk-Tchebichef Transform (DCKTKT) to provide a better level of representation of the signal in the delay-Doppler context. It uses a depth-pipelined and fully parallel hardware design to run important operations like FFT/IFFT and modulation, and uses the Lyrebird Optimization Algorithm (LOA) to allocate resources optimally. The implementation results on the platform based on 7vx485tfg1157-1 FPGA indicate that the design can achieve a peak throughput of 217.83 Tbps, with only 61,842 LUTs and 19,865 flip-flops, with the highest possible clock frequency being 168.37&#xa0;MHz. This architecture achieves superior performance over conventional OTFS designs by reducing latency, minimizing logic complexity, and delivering high-speed, energy-efficient signal processing under dynamic multi-path fading conditions.</p>

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Low-Complexity VLSI architecture for OTFS transceiver under Fully Parallel and Pipelined Hardware Architecture using Cosine-Krawtchouk Point-wise Discrete Activations Tchebichef Steerable Lyrebird Convolutional Transforms Networks

  • 期刊论文

  • 发表日期：

    2026年7月2日

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  • Balamurugan Rajangam,
  • Maheswari Murali

摘要

Orthogonal Time Frequency Space (OTFS) modulation has gained attention as a reliable wireless communication technique, especially under high-mobility and time-varying channel conditions. However, conventional OTFS transceiver designs face significant challenges in terms of hardware complexity, low throughput, and inefficient execution in multi-path fading environments. To overcome these limitations, this paper introduces an OTFS Transceiver with Low-Complexity VLSI Architecture in A Fully Parallel and Pipelined Hardware Architecture in Cosine-Krawtchouk Point-wise Discrete Activations Tchebichef Steerable Lyrebird Convolutional Transforms Networks (CosKPWD-ATSL-CTN). The suggested CosKPWD-ATSL-CTN framework combines Point-wise Activations and Steerable Convolutional Networks (PWASCN) with Discrete Cosine-Krawtchouk-Tchebichef Transform (DCKTKT) to provide a better level of representation of the signal in the delay-Doppler context. It uses a depth-pipelined and fully parallel hardware design to run important operations like FFT/IFFT and modulation, and uses the Lyrebird Optimization Algorithm (LOA) to allocate resources optimally. The implementation results on the platform based on 7vx485tfg1157-1 FPGA indicate that the design can achieve a peak throughput of 217.83 Tbps, with only 61,842 LUTs and 19,865 flip-flops, with the highest possible clock frequency being 168.37 MHz. This architecture achieves superior performance over conventional OTFS designs by reducing latency, minimizing logic complexity, and delivering high-speed, energy-efficient signal processing under dynamic multi-path fading conditions.