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<p>The Complementary Metal-Oxide Semiconductor–Very Large Scale Integration (CMOS-VLSI) scalability has introduced increased power density and energy consumption in recent years. Modeling complex relationships among integrated circuit components remains challenging. Existing models fail to capture interactions under varying conditions, limiting accurate power prediction. In this paper, a Power-Aware Lorentz-Equivariant Quantum Graph Neural Network for Accurate Power Estimation in CMOS-VLSI Circuits (PLEQGN-VLSI-RPEE) is proposed. Initially, ISCAS’89 benchmark circuits are modeled as directed graphs, capturing both combinational and sequential behaviors through node features such as switching activity and electrical parameters. Then, Power-Aware Lorentz-Equivariant Quantum Graph Neural Network (PLEQGN) estimates power by capturing spatial-temporal dependencies via Lorentz-equivariant message passing and quantum-inspired encoding, while power-aware attention emphasizes high switching activity nodes to improve estimation accuracy in combinational and sequential circuits. Finally, House Swallow Optimization (HSO) is employed to optimize network weights and biases, minimizing estimation error. The proposed PLEQGN-VLSI-RPEE method is implemented in Python, and its performance is evaluated using several metrics such as Mean Square Error (MSE), correlation coefficient, power consumption prediction, and time complexity. The proposed PLEQGN-VLSI-RPEE approach achieved superior results, with an MSE of 0.23 mW, a correlation coefficient of 0.96, and a predicted power of 0.89 mW, thereby outstripping existing methods.</p>

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Power-aware Lorentz-equivariant quantum graph neural network for accurate power estimation in CMOS-VLSI circuits

  • 期刊论文

  • 发表日期：

    2026年7月17日

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  • Satyaraj D,
  • Vigneash L,
  • Priyadharsini,
  • Kondru Venkata Murali Siva Prasad

摘要

The Complementary Metal-Oxide Semiconductor–Very Large Scale Integration (CMOS-VLSI) scalability has introduced increased power density and energy consumption in recent years. Modeling complex relationships among integrated circuit components remains challenging. Existing models fail to capture interactions under varying conditions, limiting accurate power prediction. In this paper, a Power-Aware Lorentz-Equivariant Quantum Graph Neural Network for Accurate Power Estimation in CMOS-VLSI Circuits (PLEQGN-VLSI-RPEE) is proposed. Initially, ISCAS’89 benchmark circuits are modeled as directed graphs, capturing both combinational and sequential behaviors through node features such as switching activity and electrical parameters. Then, Power-Aware Lorentz-Equivariant Quantum Graph Neural Network (PLEQGN) estimates power by capturing spatial-temporal dependencies via Lorentz-equivariant message passing and quantum-inspired encoding, while power-aware attention emphasizes high switching activity nodes to improve estimation accuracy in combinational and sequential circuits. Finally, House Swallow Optimization (HSO) is employed to optimize network weights and biases, minimizing estimation error. The proposed PLEQGN-VLSI-RPEE method is implemented in Python, and its performance is evaluated using several metrics such as Mean Square Error (MSE), correlation coefficient, power consumption prediction, and time complexity. The proposed PLEQGN-VLSI-RPEE approach achieved superior results, with an MSE of 0.23 mW, a correlation coefficient of 0.96, and a predicted power of 0.89 mW, thereby outstripping existing methods.