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<p>Power reduction and stability enhancement remain critical challenges in advanced SRAM design. This paper presents a comparative study of conventional, stacked, and Multi-Threshold CMOS (MTCMOS) 10T SRAM cells implemented in 90 nm CMOS technology. The stacked configuration leverages the stack effect to suppress subthreshold leakage and mitigate drain-induced barrier lowering, achieving ultra-low standby power with moderate read/write delays. In contrast, the MTCMOS architecture employs low and high-threshold transistors with sleep-based power gating, reducing leakage while maintaining high-speed operation. Simulation results show that the stacked 10T SRAM achieves read static noise margin (RSNM), hold static noise margin (HSNM), and write static noise margin (WSNM) values of 470 mV, 570 mV, and 230 mV, respectively, with read/write power consumption of 0.03 <InlineEquation ID="IEq1"> <EquationSource Format="TEX">\(\upmu\)</EquationSource> </InlineEquation>W and 0.77 <InlineEquation ID="IEq2"> <EquationSource Format="TEX">\(\upmu\)</EquationSource> </InlineEquation>W, respectively. The MTCMOS-based design demonstrates superior stability (RSNM: 616 mV, HSNM: 660 mV, WSNM: 1 V) and faster access times (read: 50 ps, write: 70 ps) at higher dynamic power. Total power consumption is 78.7 <InlineEquation ID="IEq3"> <EquationSource Format="TEX">\(\upmu\)</EquationSource> </InlineEquation>W for stacked SRAM and 13.8 <InlineEquation ID="IEq4"> <EquationSource Format="TEX">\(\upmu\)</EquationSource> </InlineEquation>W for MTCMOS SRAM. N-curve analysis, process corner evaluation, Post Layout with DRC/LVS checked, and Monte Carlo simulations confirm robust operation under variability. Overall, MTCMOS SRAM is optimal for ultra-low-power applications and better suited for high-speed, high-stability systems.</p>

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Low power and highly stable 10 T SRAM cell design using stacked and MTCMOS techniques

  • 期刊论文

  • 发表日期：

    2026年5月21日

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  • Md. Mozahidul Islam,
  • Fariha Zaman,
  • Md. Tawfiq Amin

摘要

Power reduction and stability enhancement remain critical challenges in advanced SRAM design. This paper presents a comparative study of conventional, stacked, and Multi-Threshold CMOS (MTCMOS) 10T SRAM cells implemented in 90 nm CMOS technology. The stacked configuration leverages the stack effect to suppress subthreshold leakage and mitigate drain-induced barrier lowering, achieving ultra-low standby power with moderate read/write delays. In contrast, the MTCMOS architecture employs low and high-threshold transistors with sleep-based power gating, reducing leakage while maintaining high-speed operation. Simulation results show that the stacked 10T SRAM achieves read static noise margin (RSNM), hold static noise margin (HSNM), and write static noise margin (WSNM) values of 470 mV, 570 mV, and 230 mV, respectively, with read/write power consumption of 0.03 \(\upmu\) W and 0.77 \(\upmu\) W, respectively. The MTCMOS-based design demonstrates superior stability (RSNM: 616 mV, HSNM: 660 mV, WSNM: 1 V) and faster access times (read: 50 ps, write: 70 ps) at higher dynamic power. Total power consumption is 78.7 \(\upmu\) W for stacked SRAM and 13.8 \(\upmu\) W for MTCMOS SRAM. N-curve analysis, process corner evaluation, Post Layout with DRC/LVS checked, and Monte Carlo simulations confirm robust operation under variability. Overall, MTCMOS SRAM is optimal for ultra-low-power applications and better suited for high-speed, high-stability systems.