Recently junctionless transistors have gained popularity due to lower fabrication complexity than conventional physically doped transistors. In this work, we have presented gate underlapped GaAs on insulator (GOI) Junctionless(JL) FinFET considering 20nm channel length. The gate underlap engineering has been performed at both the source side and the drain side to improve key short channel effects like leakage current and sub-threshold swing. The DC performances of the proposed device are compared with the conventional Silicon-based SOI JL FinFET and the proposed device provides significant improvement in terms of \(\text {I}_\text {ON}\) (76%), \(\text {I}_\text {OFF}\) (3255 times), \(\text {I}_\text {ON}\) / \(\text {I}_\text {OFF}\) ( 13895 times), and SS (5.80%) than the conventional Silicon-based SOI JL FinFET. The Analog/RF Figures of Merits such as Transconductance, Cut-off frequency, Gain-Bandwidth Product, Transit time, Transconductance Generation Factor, and Transconductance Frequency Product of the proposed device are studied considering the impact of temperature variations from 300K to 500K. Furthermore, several linearity parameters such as higher-order transconductances ( \(\text {g}_\text {m2}\) , \(\text {g}_\text {m3}\) ) and voltage intersection points (VIP2, VIP3) of the proposed device are evaluated for a wide range of temperature variations. In addition, the circuit-level performances are also investigated by designing the proposed device-based Current-Starved Voltage Controlled Oscillator (CS VCO) using the Cadence Virtuoso tool. The proposed FinFET-based CS VCO provides a wider tuning range of 99% which is 8% better than other recently published work. The proposed device-based CS VCO also provides a higher VCO gain of 9.91 GHz/V. Thus, the proposed device can be better suitable for Radio-Frequency circuit-level applications.
