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<p>Network-on-Chip (NoC) has emerged as a promising interconnection framework for Multi-Processor System-on-Chips (MPSoCs) due to its efficiency and scalability. However, in deep submicron technologies, NoCs are increasingly susceptible to faults in critical components such as links and routers, leading to reduced system performance and reliability. This paper presents a novel Deep Q-Network (DQN)-based Fault-Tolerant Routing (DQN-FTR) algorithm designed to optimize routing decisions in mesh-based NoC architectures. The proposed approach is evaluated against traditional Q-learning and static routing techniques under varying traffic patterns and fault conditions. A SystemC-based cycle-accurate NoC simulator is used to conduct extensive simulations across different mesh sizes and fault scenarios. Additionally, the algorithm’s real-time performance is validated using the Zynq UltraScale+ MPSoC ZCU104 Evaluation Kit. Experimental results demonstrate that the DQN-FTR algorithm significantly outperforms Q-learning and static routing in terms of latency, throughput, and fault tolerance, providing a robust and scalable solution for fault-tolerant routing in NoCs.</p>

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Reinforcement learning-driven fault-tolerant routing for mesh-based Network-on-Chip architectures

  • 期刊论文

  • 发表日期：

    2026年4月7日

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  • Challa Muralikrishna Yadav,
  • B. Naresh Kumar Reddy

摘要

Network-on-Chip (NoC) has emerged as a promising interconnection framework for Multi-Processor System-on-Chips (MPSoCs) due to its efficiency and scalability. However, in deep submicron technologies, NoCs are increasingly susceptible to faults in critical components such as links and routers, leading to reduced system performance and reliability. This paper presents a novel Deep Q-Network (DQN)-based Fault-Tolerant Routing (DQN-FTR) algorithm designed to optimize routing decisions in mesh-based NoC architectures. The proposed approach is evaluated against traditional Q-learning and static routing techniques under varying traffic patterns and fault conditions. A SystemC-based cycle-accurate NoC simulator is used to conduct extensive simulations across different mesh sizes and fault scenarios. Additionally, the algorithm’s real-time performance is validated using the Zynq UltraScale+ MPSoC ZCU104 Evaluation Kit. Experimental results demonstrate that the DQN-FTR algorithm significantly outperforms Q-learning and static routing in terms of latency, throughput, and fault tolerance, providing a robust and scalable solution for fault-tolerant routing in NoCs.