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<p>Carbon nanotube field-effect transistor (CNTFET) technology has evolved as a promising substitute to metal oxide semiconductor field-effect transistor (MOSFET) technology. CNTFET technology provides excellent electrical properties like greater carrier mobility, ballistic transport, and variable threshold. In MOSFET, the short-channel effects become dominant at lower technology nodes due to continuous device scaling, which degrades the various performance metrics. In this work, a CNTFET-based static random-access memory (SRAM) cell is designed using the low-power input-controlled stack (ICS) technique. The proposed SRAM (ICS-SRAM) cell exhibits enhanced performance and stability when compared to existing designs. The proposed ICS-SRAM is simulated using the Stanford 32&#xa0;nm CNTFET model at a supply voltage of 0.7&#xa0;V to evaluate the different performance metrics. The simulation results indicate that the ICS-SRAM cell achieves improvement in average power dissipation and energy efficiency compared to existing designs. The speed of SRAM cell is also improved with ICS technique. The stability analysis is conducted for the ICS-SRAM cell using the butterfly and the N-curve methods. The variability analysis of the ICS-SRAM cell is performed for the static noise margin (SNM) metric under process, voltage, and temperature (PVT) variations to evaluate its reliability for 1000 samples using Monte Carlo simulations. The Kolmogorov-Smirnov (K-S) test for the Monte Carlo results has been performed using MATLAB.</p>

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Comprehensive analysis of CNTFET-based low-power SRAM cell

  • 期刊论文

  • 发表日期：

    2026年3月2日

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  • Ekta Jolly,
  • Vijay Kumar Sharma,
  • Anil Kumar Bhardwaj

摘要

Carbon nanotube field-effect transistor (CNTFET) technology has evolved as a promising substitute to metal oxide semiconductor field-effect transistor (MOSFET) technology. CNTFET technology provides excellent electrical properties like greater carrier mobility, ballistic transport, and variable threshold. In MOSFET, the short-channel effects become dominant at lower technology nodes due to continuous device scaling, which degrades the various performance metrics. In this work, a CNTFET-based static random-access memory (SRAM) cell is designed using the low-power input-controlled stack (ICS) technique. The proposed SRAM (ICS-SRAM) cell exhibits enhanced performance and stability when compared to existing designs. The proposed ICS-SRAM is simulated using the Stanford 32 nm CNTFET model at a supply voltage of 0.7 V to evaluate the different performance metrics. The simulation results indicate that the ICS-SRAM cell achieves improvement in average power dissipation and energy efficiency compared to existing designs. The speed of SRAM cell is also improved with ICS technique. The stability analysis is conducted for the ICS-SRAM cell using the butterfly and the N-curve methods. The variability analysis of the ICS-SRAM cell is performed for the static noise margin (SNM) metric under process, voltage, and temperature (PVT) variations to evaluate its reliability for 1000 samples using Monte Carlo simulations. The Kolmogorov-Smirnov (K-S) test for the Monte Carlo results has been performed using MATLAB.