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<p>Random number generators (RNGs) are crucial in various fields like radar anti-jamming, cryptographic security, and physical testing. These fields demand that RNGs provide high randomness, unpredictability, and throughput. This paper presents a combination of true random number generator (TRNG) and the Lorenz chaotic system to develop a novel hybrid random number generator (HRNG) on FPGA. By periodically updating the initial value of the Lorenz chaotic system with true random numbers, the HRNG is able to realize the unpredictability of chaotic systems. The TRNG employs ring oscillator (RO) as the entropy source, and utilizes carry-logic primitives within FPGA to improve entropy extraction efficiency. The proposed HRNG is implemented on Xilinx FPGAs with resource-saving and data throughput features and achieves 484.86 Mbps and 400 Mbps throughput on Xilinx Kintex-7 and Spartan-6 FPGAs, respectively. The random numbers yielded by the HRNG are verified by the NIST 800 − 22 test and GM/T 0005-2021 test, indicating that the HRNG output meets cryptographic standards and exhibits adequate randomness.</p>

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Implementation of hybrid random number generator on FPGA: Combining lorenz chaotic system with carry chain based ring oscillator

  • 期刊论文

  • 发表日期：

    2026年3月10日

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  • Baoshuo Fan,
  • Xiangye Zeng,
  • Jingyi Wang,
  • Mingming Luo,
  • Xiaoyu Li,
  • Jianfei Liu,
  • Jia Lu,
  • Jie Ma

摘要

Random number generators (RNGs) are crucial in various fields like radar anti-jamming, cryptographic security, and physical testing. These fields demand that RNGs provide high randomness, unpredictability, and throughput. This paper presents a combination of true random number generator (TRNG) and the Lorenz chaotic system to develop a novel hybrid random number generator (HRNG) on FPGA. By periodically updating the initial value of the Lorenz chaotic system with true random numbers, the HRNG is able to realize the unpredictability of chaotic systems. The TRNG employs ring oscillator (RO) as the entropy source, and utilizes carry-logic primitives within FPGA to improve entropy extraction efficiency. The proposed HRNG is implemented on Xilinx FPGAs with resource-saving and data throughput features and achieves 484.86 Mbps and 400 Mbps throughput on Xilinx Kintex-7 and Spartan-6 FPGAs, respectively. The random numbers yielded by the HRNG are verified by the NIST 800 − 22 test and GM/T 0005-2021 test, indicating that the HRNG output meets cryptographic standards and exhibits adequate randomness.