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<p>In this paper, we introduce a novel four-stage self-cascode charge pump aimed at achieving high efficiency and elevated voltage stimulation. The use of a self-cascode structure significantly reduces ripple and power consumption (10 times lower in comparison with similar structure). Additionally, integrating the self-cascode architecture in the proposed charge pump greatly enhances circuit stability during rise and fall time increments. The new design effectively mitigates the impacts of charge injection and clock feedthrough on the output node. The charge pump is implemented in TSMC 180&#xa0;nm 1.8&#xa0;V/3.3&#xa0;V LV CMOS technology. The results demonstrate outputs of 11.04&#xa0;V and 12.5&#xa0;V with input voltages of 2.5&#xa0;V and 3&#xa0;V, respectively, using 2pF load and pumping capacitors. The circuit achieves a low ripple amplitude of 50 mV, 5 times lower than similar work, when operating at a 5&#xa0;MHz clock frequency with rise and fall times of 1.2 ns. Each individual stage has a gain of 1.45, and the overall gain of the charge pump circuit is 4.5. With its constant and regulated output and low current consumption, this innovative charge pump design is well-suited for low-power biomedical applications in CMOS processes.</p>

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A new low-power low-ripple charge pump based on self-cascode configuration

  • 期刊论文

  • 发表日期：

    2026年1月31日

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  • Mostafa Katebi,
  • Abbas Erfanian,
  • Mohammad Azim Karami,
  • Mohamad Sawan

摘要

In this paper, we introduce a novel four-stage self-cascode charge pump aimed at achieving high efficiency and elevated voltage stimulation. The use of a self-cascode structure significantly reduces ripple and power consumption (10 times lower in comparison with similar structure). Additionally, integrating the self-cascode architecture in the proposed charge pump greatly enhances circuit stability during rise and fall time increments. The new design effectively mitigates the impacts of charge injection and clock feedthrough on the output node. The charge pump is implemented in TSMC 180 nm 1.8 V/3.3 V LV CMOS technology. The results demonstrate outputs of 11.04 V and 12.5 V with input voltages of 2.5 V and 3 V, respectively, using 2pF load and pumping capacitors. The circuit achieves a low ripple amplitude of 50 mV, 5 times lower than similar work, when operating at a 5 MHz clock frequency with rise and fall times of 1.2 ns. Each individual stage has a gain of 1.45, and the overall gain of the charge pump circuit is 4.5. With its constant and regulated output and low current consumption, this innovative charge pump design is well-suited for low-power biomedical applications in CMOS processes.