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<p>In this work a low-power analog integrated image edge detector employing squarer and theshold circuits is presented. A hardware-friendly approximation of the Robert’s Cross operator serves as the foundation for the operation of this architecture. The system-level implementation can be easily adapted to accommodate different image resolutions. As a result, larger integrated smart sensor systems can use the proposed architecture as a building block. Four medium-resolution images were used to test the edge detector, which consumed only 24 nW per pixel while achieving an average Peak Signal-to-Noise Ratio (PSNR) of 27.3 dB and a Structural Similarity Index Metric (SSIM) of 0.82. An interesting characteristic is the high computational speed equal to 320,000 frames per second. Monte Carlo simulations, incorporating process variations and mismatches, along with corner-case analysis, are conducted to verify the robustness of the proposed edge detector. A comparative analysis of post-layout simulation results with an equivalent software-based edge detector and existing literature validates the accuracy and reliable operation of the proposed design. Both schematic and post-layout simulations are carried out using the Cadence IC suite with a 90 nm CMOS process.</p>

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A current-mode, low-power, area-efficient analog-hardware squarer-based edge detector

  • 期刊论文

  • 出版模式：

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  • 发表日期：

    2026年1月31日

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  • Vassilis Alimisis,
  • Konstantinos Cheliotis,
  • Anna Mylona,
  • Zisis Foufas,
  • Vasileios Moustakas,
  • Paul P. Sotiriadis

摘要

In this work a low-power analog integrated image edge detector employing squarer and theshold circuits is presented. A hardware-friendly approximation of the Robert’s Cross operator serves as the foundation for the operation of this architecture. The system-level implementation can be easily adapted to accommodate different image resolutions. As a result, larger integrated smart sensor systems can use the proposed architecture as a building block. Four medium-resolution images were used to test the edge detector, which consumed only 24 nW per pixel while achieving an average Peak Signal-to-Noise Ratio (PSNR) of 27.3 dB and a Structural Similarity Index Metric (SSIM) of 0.82. An interesting characteristic is the high computational speed equal to 320,000 frames per second. Monte Carlo simulations, incorporating process variations and mismatches, along with corner-case analysis, are conducted to verify the robustness of the proposed edge detector. A comparative analysis of post-layout simulation results with an equivalent software-based edge detector and existing literature validates the accuracy and reliable operation of the proposed design. Both schematic and post-layout simulations are carried out using the Cadence IC suite with a 90 nm CMOS process.