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<p>This work introduces a novel quad-tail-cell-based Dynamic Current Mode Logic (DyCML) architecture to implement three-input logic function. Existing quad-tail-cell-based MOS Current Mode Logic (MCML) designs rely on a static current source, resulting in continuous static power dissipation. In contrast, the proposed DyCML approach eliminates the static current source and offers the advantages of dynamic logic, leading to reduced power consumption, lower delay, and minimized switching current, while supporting high-speed performance at lower supply voltages. To demonstrate the approach, a three-input XOR gate, an essential building block in digital systems, is designed and optimized using Taguchi’s design of experiments (DoE) method and ANOVA statistical analysis. The optimized design achieves 26.29 µW power dissipation, 185.5 ps propagation delay, and a power-delay product (PDP) of 4.87 fJ. The circuit is implemented and simulated in Cadence Virtuoso using GPDK 45&#xa0;nm CMOS technology at a 1.1&#xa0;V supply voltage. Compared to the existing quad-tail-cell-based MCML XOR gate, the proposed design delivers 34.45% lower delay, 88.26% lower power, and a 92.31% improvement in PDP. Post-layout simulations show an area of 208.98&#xa0;μm², while robustness is confirmed through Monte Carlo and PVT variation analyses. The methodology is further extended to a generic gate architecture for realizing larger logic functions, such as a full adder and a 4 × 1 multiplexer.</p>

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Design and optimization of a Quad-Tail-Cell dynamic MCML for low-power three-input logic using Taguchi and ANOVA methods

  • 期刊论文

  • 发表日期：

    2025年12月8日

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  • Dheeraj Singh Rajput,
  • Bharat Choudhary,
  • Dharmendar Boolchandani

摘要

This work introduces a novel quad-tail-cell-based Dynamic Current Mode Logic (DyCML) architecture to implement three-input logic function. Existing quad-tail-cell-based MOS Current Mode Logic (MCML) designs rely on a static current source, resulting in continuous static power dissipation. In contrast, the proposed DyCML approach eliminates the static current source and offers the advantages of dynamic logic, leading to reduced power consumption, lower delay, and minimized switching current, while supporting high-speed performance at lower supply voltages. To demonstrate the approach, a three-input XOR gate, an essential building block in digital systems, is designed and optimized using Taguchi’s design of experiments (DoE) method and ANOVA statistical analysis. The optimized design achieves 26.29 µW power dissipation, 185.5 ps propagation delay, and a power-delay product (PDP) of 4.87 fJ. The circuit is implemented and simulated in Cadence Virtuoso using GPDK 45 nm CMOS technology at a 1.1 V supply voltage. Compared to the existing quad-tail-cell-based MCML XOR gate, the proposed design delivers 34.45% lower delay, 88.26% lower power, and a 92.31% improvement in PDP. Post-layout simulations show an area of 208.98 μm², while robustness is confirmed through Monte Carlo and PVT variation analyses. The methodology is further extended to a generic gate architecture for realizing larger logic functions, such as a full adder and a 4 × 1 multiplexer.