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<p>Effective partitioning and floor planning are key issues in VLSI circuit design that directly influence performance, power consumption, and area use. The conventional methodologies tend to compromise on these factors poorly, particularly in large-scale and complicated circuit structures. To overcome this problem, a novel framework known as Dilated Causal Convolution Guided with Multi-head Decision Self-Transformer Network (D2C-GMH-DSTN) is presented. This architecture combines Dilated Causal Convolution with multi-head self-attention and is augmented by a Critic-Guided Decision Transformer. To optimize its decision-making further, the Meerkat Optimization Algorithm (MOA) is utilized. Experimental verification on typical MCNC benchmark circuits verifies the excellence of the presented approach. On the circuits S1196, S1238, S3350, and S8378, the method attains an average speed of 98.75 ms, a minimum average wire length of 28.75&#xa0;m, and less power consumption as low as 1.175&#xa0;W, surpassing state-of-the-art baseline methods on all dimensions. The technique offers a scalable and resilient solution with high precision, significantly enhancing design optimization results.</p>

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D2C-GMH-DSTN: A high-precision partitioning and floor planning framework for VLSI circuits using dilated causal convolution and multi-head decision transformers

  • 期刊论文

  • 发表日期：

    2025年12月29日

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  • K K Senthilkumar,
  • V. Magesh,
  • S. S. Saravana Kumar,
  • Badiganchela Shiva Kumar

摘要

Effective partitioning and floor planning are key issues in VLSI circuit design that directly influence performance, power consumption, and area use. The conventional methodologies tend to compromise on these factors poorly, particularly in large-scale and complicated circuit structures. To overcome this problem, a novel framework known as Dilated Causal Convolution Guided with Multi-head Decision Self-Transformer Network (D2C-GMH-DSTN) is presented. This architecture combines Dilated Causal Convolution with multi-head self-attention and is augmented by a Critic-Guided Decision Transformer. To optimize its decision-making further, the Meerkat Optimization Algorithm (MOA) is utilized. Experimental verification on typical MCNC benchmark circuits verifies the excellence of the presented approach. On the circuits S1196, S1238, S3350, and S8378, the method attains an average speed of 98.75 ms, a minimum average wire length of 28.75 m, and less power consumption as low as 1.175 W, surpassing state-of-the-art baseline methods on all dimensions. The technique offers a scalable and resilient solution with high precision, significantly enhancing design optimization results.