Scholarlink

<p>This paper demonstrates the device-circuit co-design of a novel non-volatile latch utilizing 20&#xa0;nm channel length silicon-on-insulator (SOI) based junctionless (JL) ferroelectric field effect transistor (FEFET). Through a combination of experimentally calibrated models and TCAD-based mixed-mode simulations, JL FEFET memory devices are shown to be effective in non-volatile latch applications. Firstly, a device-level performance assessment is carried out to obtain the programming speed, data retention, and endurance. The results demonstrate the potential of 20&#xa0;nm channel length JL FEFET for non-volatile logic-in-memory applications, showcasing their ability to provide higher memory density, improved scalability, and reduced power consumption compared to conventional memory technologies. Herein, junctionless ferroelectric field effect transistor with a Metal-Ferroelectric-Insulator-Semiconductor gate stack of a 10&#xa0;nm Hf<sub>0.4</sub>Zr<sub>0.6</sub>O<sub>2</sub> (HZO) thickness is demonstrated, which attains a memory window of 0.9&#xa0;V. This paper further investigates JL FEFET-based novel non-volatile latch, which has an automatic load-store mechanism.</p>

错误：搜索内容不能为空，请输入英文关键词
错误：关键词超出字数限制，请精简
高级检索

Device circuit co-design of novel non-volatile latch using junctionless ferroelectric FET

  • 期刊论文

  • 发表日期：

    2025年12月27日

查看全文
  • Roopesh Singh,
  • Alok Kumar Tripathi,
  • Shivam Verma

摘要

This paper demonstrates the device-circuit co-design of a novel non-volatile latch utilizing 20 nm channel length silicon-on-insulator (SOI) based junctionless (JL) ferroelectric field effect transistor (FEFET). Through a combination of experimentally calibrated models and TCAD-based mixed-mode simulations, JL FEFET memory devices are shown to be effective in non-volatile latch applications. Firstly, a device-level performance assessment is carried out to obtain the programming speed, data retention, and endurance. The results demonstrate the potential of 20 nm channel length JL FEFET for non-volatile logic-in-memory applications, showcasing their ability to provide higher memory density, improved scalability, and reduced power consumption compared to conventional memory technologies. Herein, junctionless ferroelectric field effect transistor with a Metal-Ferroelectric-Insulator-Semiconductor gate stack of a 10 nm Hf0.4Zr0.6O2 (HZO) thickness is demonstrated, which attains a memory window of 0.9 V. This paper further investigates JL FEFET-based novel non-volatile latch, which has an automatic load-store mechanism.