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<p>This paper presents a race-free cascaded dynamic current mode logic (DyCML) derived from NORA-based CMOS dynamic circuits. Cascading two stages of DyCML gates poses the challenge of erroneous evaluation between stages. To address this, two traditional cascading mechanisms, one using a clock delay scheme and the other employing a self-timing scheme, both require intermediary circuits, such as inverters or buffers, between stages. This paper proposes a new complementary DyCML for the NORA-based cascaded technique, which is completely race-free, regardless of the overlap period of the two complementary clock signals. The proposed technique eliminates the need for intermediary circuitry, thereby resolving the issue of erroneous evaluation. The new NORA-based technique enhances performance, including reductions in delay, power consumption, and area. The proposed NORA-based DyCML circuit was optimized using a combination of Taguchi and ANOVA statistical techniques. Following this optimization process, the circuit achieved a delay of 121.8 ps, a power consumption of 6.11 µW, and a power-delay product (PDP) of 0.744 fJ. Simulations conducted in Cadence Virtuoso using GPDK 45&#xa0;nm CMOS technology at a 1&#xa0;V supply voltage demonstrate improvements of 69.55%, 17.85%, 74.97%, and 27.90% in delay, power consumption, power-delay product, and area, respectively, compared to the existing design. Post-layout simulations further validate the performance parameters, while Monte Carlo simulations and process, voltage, and temperature (PVT) variations confirm the robustness of the proposed circuit. Overall, the proposed NORA-based DyCML technique offers significant advantages in performance and area efficiency, making it a viable solution for low-power, high-performance logic circuits.</p>

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An efficient race-free dynamic MCML design for multistage applications

  • 期刊论文

  • 发表日期：

    2025年11月15日

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  • Dheeraj Singh Rajput,
  • Bharat Choudhary,
  • Dharmendar Boolchandani,
  • Archana Singhal

摘要

This paper presents a race-free cascaded dynamic current mode logic (DyCML) derived from NORA-based CMOS dynamic circuits. Cascading two stages of DyCML gates poses the challenge of erroneous evaluation between stages. To address this, two traditional cascading mechanisms, one using a clock delay scheme and the other employing a self-timing scheme, both require intermediary circuits, such as inverters or buffers, between stages. This paper proposes a new complementary DyCML for the NORA-based cascaded technique, which is completely race-free, regardless of the overlap period of the two complementary clock signals. The proposed technique eliminates the need for intermediary circuitry, thereby resolving the issue of erroneous evaluation. The new NORA-based technique enhances performance, including reductions in delay, power consumption, and area. The proposed NORA-based DyCML circuit was optimized using a combination of Taguchi and ANOVA statistical techniques. Following this optimization process, the circuit achieved a delay of 121.8 ps, a power consumption of 6.11 µW, and a power-delay product (PDP) of 0.744 fJ. Simulations conducted in Cadence Virtuoso using GPDK 45 nm CMOS technology at a 1 V supply voltage demonstrate improvements of 69.55%, 17.85%, 74.97%, and 27.90% in delay, power consumption, power-delay product, and area, respectively, compared to the existing design. Post-layout simulations further validate the performance parameters, while Monte Carlo simulations and process, voltage, and temperature (PVT) variations confirm the robustness of the proposed circuit. Overall, the proposed NORA-based DyCML technique offers significant advantages in performance and area efficiency, making it a viable solution for low-power, high-performance logic circuits.