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<p>Nowadays, digital color images are most frequently used in applications like online security, healthcare, and military operations, so a highly secure method for encrypting and decrypting these digital color images is required. In this paper, a new method based on multiple TRNGs architectures is proposed for generating random keys for performing encryption and decryption of digital color images. Four TRNG architectures outputs: Elementary ring oscillators based on TRNG1, TERO (Transition Effect Ring Oscillator)TRNG 2,Thermal Noise-based TRNG 3,TRNG4 based on ADPLL and 1 DFF output as an entropy source are XORed, sampled by a DFF and post-processed to generate true random bits. These true random bits are passed to 8bit SIPO shift register circuit to generate 8-bit true random numbers. The output of SIPO is passed to the Arduino uno board at a baud rate of 9600 for storing 8bit true random numbers in a text file using CoolTerm software. The Artix7 FPGA board is used for implementing the proposed TRNG architecture. The Xilinx Vivado 2015.2 tool is used for designing the proposed TRNG architecture and performing encryption and decryption. The proposed TRNG architecture passes the NIST SP 800 − 22 test, consumes 0.073&#xa0;W of power, achieves a throughput value of 618.42Mbps and its efficiency (Mbps/LUTS) is 3.989.</p>

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Multiple TRNGs based on random number generation and its application in color image encryption and decryption

  • 期刊论文

  • 发表日期：

    2025年11月13日

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  • Manoj Kumar

摘要

Nowadays, digital color images are most frequently used in applications like online security, healthcare, and military operations, so a highly secure method for encrypting and decrypting these digital color images is required. In this paper, a new method based on multiple TRNGs architectures is proposed for generating random keys for performing encryption and decryption of digital color images. Four TRNG architectures outputs: Elementary ring oscillators based on TRNG1, TERO (Transition Effect Ring Oscillator)TRNG 2,Thermal Noise-based TRNG 3,TRNG4 based on ADPLL and 1 DFF output as an entropy source are XORed, sampled by a DFF and post-processed to generate true random bits. These true random bits are passed to 8bit SIPO shift register circuit to generate 8-bit true random numbers. The output of SIPO is passed to the Arduino uno board at a baud rate of 9600 for storing 8bit true random numbers in a text file using CoolTerm software. The Artix7 FPGA board is used for implementing the proposed TRNG architecture. The Xilinx Vivado 2015.2 tool is used for designing the proposed TRNG architecture and performing encryption and decryption. The proposed TRNG architecture passes the NIST SP 800 − 22 test, consumes 0.073 W of power, achieves a throughput value of 618.42Mbps and its efficiency (Mbps/LUTS) is 3.989.