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<p>This paper presents a low-power and high performance decision tree classifier for biomedical applications. The proposed architecture consists of Current Comparator circuits, ReLu circuits, Gaussian function circuits, analog multipliers, Current Mirrors and argmax operator. All the circuits operate in the sub-threshold region in order to achieve power-efficiency. The principles of the architecture are thoroughly described and realized in an energy-efficient set-up that consumes less than 956&#xa0;nW and operates on low supply rails of 0.6&#xa0;V. When tested on real-world biomedical classification tasks, the proposed design achieved a classification accuracy exceeding <InlineEquation ID="IEq1"> <InlineMediaObject> <ImageObject Color="BlackWhite" FileRef="10470_2025_2481_Article_IEq1.gif" Format="GIF" Height="16" Rendition="HTML" Resolution="72" Type="Linedraw" Width="51" /> </InlineMediaObject> <EquationSource Format="TEX">\(91.30\%\)</EquationSource> </InlineEquation>. The Cadence IC Suite was used for the schematic design and layout, and the implementation was carried out using 90&#xa0;nm CMOS technology. The robustness of the classifier was evaluated through corner-case analysis and Monte Carlo simulations, accounting for process variations and mismatches. The accuracy and reliable performance of the proposed architecture were confirmed by comparing post-layout simulation results with those of a software-based classifier and relevant prior studies.</p>

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An analog ReLu-based decision tree circuit architecture for biomedical applications

  • 期刊论文

  • 出版模式：

    开放获取

  • 发表日期：

    2025年8月28日

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  • Vassilis Alimisis,
  • Vasileios Moustakas,
  • Konstantinos Cheliotis,
  • Anna Mylona,
  • Paul P. Sotiriadis

摘要

This paper presents a low-power and high performance decision tree classifier for biomedical applications. The proposed architecture consists of Current Comparator circuits, ReLu circuits, Gaussian function circuits, analog multipliers, Current Mirrors and argmax operator. All the circuits operate in the sub-threshold region in order to achieve power-efficiency. The principles of the architecture are thoroughly described and realized in an energy-efficient set-up that consumes less than 956 nW and operates on low supply rails of 0.6 V. When tested on real-world biomedical classification tasks, the proposed design achieved a classification accuracy exceeding \(91.30\%\) . The Cadence IC Suite was used for the schematic design and layout, and the implementation was carried out using 90 nm CMOS technology. The robustness of the classifier was evaluated through corner-case analysis and Monte Carlo simulations, accounting for process variations and mismatches. The accuracy and reliable performance of the proposed architecture were confirmed by comparing post-layout simulation results with those of a software-based classifier and relevant prior studies.