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<p>A general methodology for designing analog integrated  artificial neural networks is presented in this work. Each high-level architecture is composed of different analog integrated circuits operating in the sub-threshold region. Modularity and scalability are key considerations in the design of each implementation, enabling successful adaptation to changes in classification parameters. The operating principles of each neural network are thoroughly explained, and the proposed designs are implemented as fully adjustable, low-power, low-voltage systems targeted at electrical impedance tomography applications. This design methodology was implemented using the Cadence IC Suite for both schematic design and simulation, employing a TSMC 90&#xa0;nm CMOS process. During the verification stage, simulation results were meticulously compared with software-based implementations of each neural network. The comparison study and simulation results validate the proposed design methodology. Monte Carlo simulations, incorporating process variations and mismatches, along with corner-case analysis, are conducted to verify the robustness of the design methodology.</p>

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A design methodology for analog integrated artificial neural networks circuits: architectures, design and training

  • 期刊论文

  • 出版模式：

    开放获取

  • 发表日期：

    2025年8月22日

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  • Vassilis Alimisis,
  • Konstantinos Cheliotis,
  • Vasileios Moustakas,
  • Anna Mylona,
  • Christos Dimas,
  • Paul P. Sotiriadis

摘要

A general methodology for designing analog integrated  artificial neural networks is presented in this work. Each high-level architecture is composed of different analog integrated circuits operating in the sub-threshold region. Modularity and scalability are key considerations in the design of each implementation, enabling successful adaptation to changes in classification parameters. The operating principles of each neural network are thoroughly explained, and the proposed designs are implemented as fully adjustable, low-power, low-voltage systems targeted at electrical impedance tomography applications. This design methodology was implemented using the Cadence IC Suite for both schematic design and simulation, employing a TSMC 90 nm CMOS process. During the verification stage, simulation results were meticulously compared with software-based implementations of each neural network. The comparison study and simulation results validate the proposed design methodology. Monte Carlo simulations, incorporating process variations and mismatches, along with corner-case analysis, are conducted to verify the robustness of the design methodology.