DS pOTFT 8T: Analysis of Dual data aware SRAM cell employing pentacene ditch formation on BGBC OTFT and LaxNb(1-x) Oy layer for high-speed, low-leakage flexible computing devices
摘要
This work presents a novel Dual-Split Bottom Gate Bottom Contact (BGBC) 8T Static Random Access Memory (DS-pOTFT 8T SRAM) architecture featuring p+ doped pentacene ditched formation as the active channel material on LaxNb(1-x)Oy dielectric substrate. The innovative design addresses critical challenges in conventional silicon-based and organic thin-film transistor (OTFT) memory systems, including bitline (BL) leakage current, write-read conflicts, and subthreshold instability that increasingly plague System-on-Chip (SoCs) applications. Comprehensive Silvaco ATLAS simulations demonstrate exceptional performance improvements as 66% reduction in off-state leakage current compared to T6T designs and 39% versus DC8T architectures, while achieving 58% energy savings per bit operation. The dual data-aware word-line control mechanism enhances write static noise margin by 64%, increasing stability from 220 mV to 280 mV under low-voltage conditions. Read operations demonstrate 56