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<p>This paper presents a high performance current mirror with a large current mirroring range. The advantages of folded flipped voltage follower (FVF) cell and super cascode transistor are combined in proposed current mirror, which make it suitable for high performance applications. The folded FVF cell provides low resistance node which is utilized to inject the input current and therefore, proposed current mirror shows input resistance of 24.15 Ω. By employing a super cascode transistor at the output node, the output resistance is increased to 28.3 GΩ. The presented current mirror achieves bandwidth of 280&#xa0;MHz and wide current mirroring range of 0 to 500 µA. The proposed current mirror has been designed using 0.18 µm CMOS technology and simulated using spectre in Cadence Virtuoso Analog Design Environment. The physical layout is designed using Cadence Virtuoso layout XL editor. The efficiency of the proposed current mirror has been demonstrated by post-layout simulation results.</p>

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High-performance flipped voltage follower based low input resistance current mirror with wide current mirroring range and high output resistance

  • 期刊论文

  • 发表日期：

    2025年6月16日

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  • Rishikesh Pandey,
  • Caffey Jindal

摘要

This paper presents a high performance current mirror with a large current mirroring range. The advantages of folded flipped voltage follower (FVF) cell and super cascode transistor are combined in proposed current mirror, which make it suitable for high performance applications. The folded FVF cell provides low resistance node which is utilized to inject the input current and therefore, proposed current mirror shows input resistance of 24.15 Ω. By employing a super cascode transistor at the output node, the output resistance is increased to 28.3 GΩ. The presented current mirror achieves bandwidth of 280 MHz and wide current mirroring range of 0 to 500 µA. The proposed current mirror has been designed using 0.18 µm CMOS technology and simulated using spectre in Cadence Virtuoso Analog Design Environment. The physical layout is designed using Cadence Virtuoso layout XL editor. The efficiency of the proposed current mirror has been demonstrated by post-layout simulation results.