Ultra low power and fast tuning interpolator in digital controlled oscillator for all digital phase locked loop

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发表日期：

2025年6月12日

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Syaza Norfilsha Ishak,
Jahariah Sampe,
Nazrul Anuar Nayan,
Huda Abdullah,
Noor Hidayah Mohd Yunus,
Mohammad Faseehuddin

摘要

All-digital phase-locked loops (ADPLL) have become increasingly attractive to academicians and industries in system-on-chips applications due to advancements in complementary metal-oxide-semiconductor (CMOS) technology, particularly in terms of reduced power consumption and smaller chip area. In ADPLL, the most vital component is the digital oscillator design, which comprises a coarse-tuned part and a fine-tuned part. This work focuses specifically on the fine-tuning part to enhance the power dissipation performance of the digital oscillator in the ADPLL. The interpolation technique is employed in circuit design, utilizing two types of controllable inverter configurations with proper sizing of CMOS within a single stage. The interpolator fine-tuned circuit consists of seven stages and is controlled by a 6-bit phase control input. This design achieves a phase step of 6 ps to 31 ps, with a power dissipation of 0.09 $\mu$ $μ$ W at a supply voltage of 1.2 V. The circuit is implemented using the Silterra 130 nm technology process, and the post-layout design achieves a compact dimension of 0.00789 $\hbox {mm}^2$ ${mm}^{2}$ .