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<p>Wire length reduction, floor planning, and partitioning have become more difficult as a result of the VLSI circuit design industry's explosive expansion. The growing system complexity, dead space, and connection delays present important design challenges. This study presents a new hybrid optimization technique called Quantum-Inspired Reptile Search technique (QIRSA) and Hybrid Spider Wasp Optimization (SWO) to tackle these issues. The primary objective is to reduce latency, area, wire length, and power consumption by optimizing VLSI circuit partitioning and floor planning. While QIRSA shortens wire length to increase overall efficiency, the SWO component concentrates on improving floor planning and partitioning. Simulations using MCNC benchmark circuits, such as S1196, S1238, S3350, and S8378, are used to validate the suggested approach. The findings show that Hybrid-SWO-QIRSA consistently performs better than other optimization algorithms that are currently in use, including LOA-OPFP, BIOA-OPFP, SBO-OPFP, and MFOA-OPFP. More affordable and power-efficient VLSI designs are the result of the hybrid approach's successful reduction of dead space, floor plan area, and routing wire lengths. Important variables like area, latency, power consumption, and wire length demonstrate notable gains in the performance comparison. Hybrid-SWO-QIRSA is proven to be an effective optimization technique for VLSI circuit design by this research.</p>

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Hybrid-SWO-QIRSA: a novel optimization approach for VLSI circuit design with improved wirelength reduction and floor planning

  • 期刊论文

  • 发表日期：

    2025年5月5日

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  • M. Prema,
  • K. R. Kavitha

摘要

Wire length reduction, floor planning, and partitioning have become more difficult as a result of the VLSI circuit design industry's explosive expansion. The growing system complexity, dead space, and connection delays present important design challenges. This study presents a new hybrid optimization technique called Quantum-Inspired Reptile Search technique (QIRSA) and Hybrid Spider Wasp Optimization (SWO) to tackle these issues. The primary objective is to reduce latency, area, wire length, and power consumption by optimizing VLSI circuit partitioning and floor planning. While QIRSA shortens wire length to increase overall efficiency, the SWO component concentrates on improving floor planning and partitioning. Simulations using MCNC benchmark circuits, such as S1196, S1238, S3350, and S8378, are used to validate the suggested approach. The findings show that Hybrid-SWO-QIRSA consistently performs better than other optimization algorithms that are currently in use, including LOA-OPFP, BIOA-OPFP, SBO-OPFP, and MFOA-OPFP. More affordable and power-efficient VLSI designs are the result of the hybrid approach's successful reduction of dead space, floor plan area, and routing wire lengths. Important variables like area, latency, power consumption, and wire length demonstrate notable gains in the performance comparison. Hybrid-SWO-QIRSA is proven to be an effective optimization technique for VLSI circuit design by this research.