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<p>Biomedical applications like body area networks (BAN) necessitate the construction of power optimized SRAMs to enhance the batteries life at BAN nodes. In this work, we have designed one-sided near threshold 10TSRAM array for low power portable biomedical applications. The proposed near threshold 10T SRAM (PNT10T SRAM) employs a cross-connected schmitt trigger (ST) inverter and normal inverter in its cell core. The separate path for reading is also employed to eliminate the reading disturbance. The write disturbance is removed in the PNT10T SRAM by removing the trail from VDD and ground. The writing ability is improved with the use of feedback-cutting approach. The standby power dissipation of the memory is mitigated with the use a tail transistor, virtual ground (VGND). The proposed design mitigates the half-select problem due to column-based transistor controlled by CCL. To evaluate the performance, the PNT10T SRAM is compared with C6T, ST11T, ST9T, TG9T, SE9T, and SLE10T SRAM cells using FinFET 18&#xa0;nm technology at 0.6&#xa0;V power supply. The PNT10T SRAM mitigates the read power, write power, and leakage power by 51.10%, 50.57%, and 78.97%. Furthermore, the read and write static noise margins improved by 54% and 39.5% respectively, compared to conventional6T (C6T) SRAM.</p>

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Design of 32 × 32 (1 KB) SRAM array using 10T SRAM cell for portable low power biomedical applications

  • 期刊论文

  • 发表日期：

    2025年3月27日

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  • Appikatla Phani Kumar,
  • Rohit Lorenzo

摘要

Biomedical applications like body area networks (BAN) necessitate the construction of power optimized SRAMs to enhance the batteries life at BAN nodes. In this work, we have designed one-sided near threshold 10TSRAM array for low power portable biomedical applications. The proposed near threshold 10T SRAM (PNT10T SRAM) employs a cross-connected schmitt trigger (ST) inverter and normal inverter in its cell core. The separate path for reading is also employed to eliminate the reading disturbance. The write disturbance is removed in the PNT10T SRAM by removing the trail from VDD and ground. The writing ability is improved with the use of feedback-cutting approach. The standby power dissipation of the memory is mitigated with the use a tail transistor, virtual ground (VGND). The proposed design mitigates the half-select problem due to column-based transistor controlled by CCL. To evaluate the performance, the PNT10T SRAM is compared with C6T, ST11T, ST9T, TG9T, SE9T, and SLE10T SRAM cells using FinFET 18 nm technology at 0.6 V power supply. The PNT10T SRAM mitigates the read power, write power, and leakage power by 51.10%, 50.57%, and 78.97%. Furthermore, the read and write static noise margins improved by 54% and 39.5% respectively, compared to conventional6T (C6T) SRAM.