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<p>Utilised in a range of applications such as registers, counters, and state machines, the D Flip-Flop (DFF) is a flexible device that has undergone development over time with innovative design approaches to enhance power efficiency. True Single Phase Clock (TSPC) logic has constantly been a preferred option in high-speed applications. This work introduces an enhanced 14 Transistor TSPC-based positive edge-triggered Domino DFF (TSPC DomDFF) at 16&#xa0;nm with a Clock-to-Q (CQD) latency of 55.4ps, improved power consumption of 96.8nW, and salient Power Delay Product (PDP) and Energy Delay Product (EDP) as 5.36aJ and 0.297aJ-ns, respectively, at an operating voltage of 0.9&#xa0;V. It showcases the performance of a high speed and power efficient design with 32%, 77%, 85%, 94% improvement in PDP with respect to MTSPC, 26TSPC, 18T HFF, and MSDFF respectively. The results are validated through detailed robust analysis. Furthermore, the proposed 14T TSPC DomDFF is implemented to construct a 4-bit Serial-in-Serial-out (SISO) Shift Register (4-SISO SR) at operating frequency of 5&#xa0;GHz. The improved results enabled the physical layout design to be accommodated within an optimized area of 3.7µm<sup>2</sup> for the proposed circuit and 15.4µm<sup>2</sup> for the proposed application.</p>

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A novel low power high speed 14T-TSPC-DomDFF design and analysis in CMOS 16nm technology

  • 期刊论文

  • 发表日期：

    2025年3月18日

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  • Ramsha Suhail,
  • Pragya Srivastava,
  • Richa Yadav,
  • Nandini Baliyan,
  • Rewa Chaudhary

摘要

Utilised in a range of applications such as registers, counters, and state machines, the D Flip-Flop (DFF) is a flexible device that has undergone development over time with innovative design approaches to enhance power efficiency. True Single Phase Clock (TSPC) logic has constantly been a preferred option in high-speed applications. This work introduces an enhanced 14 Transistor TSPC-based positive edge-triggered Domino DFF (TSPC DomDFF) at 16 nm with a Clock-to-Q (CQD) latency of 55.4ps, improved power consumption of 96.8nW, and salient Power Delay Product (PDP) and Energy Delay Product (EDP) as 5.36aJ and 0.297aJ-ns, respectively, at an operating voltage of 0.9 V. It showcases the performance of a high speed and power efficient design with 32%, 77%, 85%, 94% improvement in PDP with respect to MTSPC, 26TSPC, 18T HFF, and MSDFF respectively. The results are validated through detailed robust analysis. Furthermore, the proposed 14T TSPC DomDFF is implemented to construct a 4-bit Serial-in-Serial-out (SISO) Shift Register (4-SISO SR) at operating frequency of 5 GHz. The improved results enabled the physical layout design to be accommodated within an optimized area of 3.7µm2 for the proposed circuit and 15.4µm2 for the proposed application.