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<p>This paper presents a Linear Phase Frequency Detector architecture (LPFD) and a Non-Linear Phase Frequency Detector (NLPFD) architecture. The proposed linear and nonlinear PFDs are free from the dead zone, blind zone, and glitches while maintaining a 360-degree detection range. The proposed Transmission Gate Voltage Divider Linear Phase Frequency Detector (TGVD-LPFD) is the best choice to provide better phase noise and reference spur for the PLL. However, the proposed transmission gate non-linear phase frequency detector (TG-NLPFD) is a better choice to have a faster locking PLL while maintaining all other better parameters. Phase-locked loop (PLL) has been implemented in a 180 nm CMOS process using these proposed linear and nonlinear PFD architectures and obtained a PLL with 2.72 GHz output frequency. A PLL built with a linear PFD has been found to offer a reference spur of <InlineEquation ID="IEq1"> <InlineMediaObject> <ImageObject Color="BlackWhite" FileRef="10470_2025_2354_Article_IEq1.gif" Format="GIF" Height="13" Rendition="HTML" Resolution="72" Type="Linedraw" Width="19" /> </InlineMediaObject> <EquationSource Format="TEX">\(-\)</EquationSource> <EquationSource Format="MATHML"><math> <mo>-</mo> </math></EquationSource> </InlineEquation>77.3 dBc and a lock time of 2.5 µs, which has been verified by modeling the PLL in the sdomain. The PLL built using non-linear PFD has been found to offer a reference spur of <InlineEquation ID="IEq3"> <InlineMediaObject> <ImageObject Color="BlackWhite" FileRef="10470_2025_2354_Article_IEq3.gif" Format="GIF" Height="13" Rendition="HTML" Resolution="72" Type="Linedraw" Width="19" /> </InlineMediaObject> <EquationSource Format="TEX">\(-\)</EquationSource> <EquationSource Format="MATHML"><math> <mo>-</mo> </math></EquationSource> </InlineEquation>74.5 dBc and a lock time of 2.3 µs, which has been verified by modeling the PLL in the state space analysis.</p>

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Glitch free transmission gate based linear and nonlinear PFD architectures for fast and low reference-spur PLL

  • 期刊论文

  • 发表日期：

    2025年2月28日

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  • N. R. Sivaraaj,
  • K. K. Abdul Majeed

摘要

This paper presents a Linear Phase Frequency Detector architecture (LPFD) and a Non-Linear Phase Frequency Detector (NLPFD) architecture. The proposed linear and nonlinear PFDs are free from the dead zone, blind zone, and glitches while maintaining a 360-degree detection range. The proposed Transmission Gate Voltage Divider Linear Phase Frequency Detector (TGVD-LPFD) is the best choice to provide better phase noise and reference spur for the PLL. However, the proposed transmission gate non-linear phase frequency detector (TG-NLPFD) is a better choice to have a faster locking PLL while maintaining all other better parameters. Phase-locked loop (PLL) has been implemented in a 180 nm CMOS process using these proposed linear and nonlinear PFD architectures and obtained a PLL with 2.72 GHz output frequency. A PLL built with a linear PFD has been found to offer a reference spur of \(-\) - 77.3 dBc and a lock time of 2.5 µs, which has been verified by modeling the PLL in the sdomain. The PLL built using non-linear PFD has been found to offer a reference spur of \(-\) - 74.5 dBc and a lock time of 2.3 µs, which has been verified by modeling the PLL in the state space analysis.