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<p>In order to enhance the data confidentiality and integrity in resource-constrained environments, an optimized hardware implementation of the Advanced Encryption Standard is proposed. An iterative architecture common for both AES-128 encryption and decryption, involving minimum hardware resources, is developed. The sub bytes and inverse sub bytes operations are realized using composite field arithmetic S-box and its inverse, respectively. The matrix constants of the inverse mixcolumns operation of decryption are expressed involving matrix constants of the mixcolumns operation of encryption. Hence, a common equation for both encryption and decryption is derived. Depending upon the requirement, encryption or decryption will be implemented with the minimum resources with appropriate control signals. The proposed work is implemented in both FPGA devices and ASIC platforms. The area occupied by the proposed architecture is 205 slices in the Virtex-5 FPGA device. The area estimate of the proposed design using 180nm technology SCL libraries is only 5644 GE, which highlights the design as a compact implementation of the AES-128 cipher and an optimal choice to ensure the safety of IoT devices.</p>

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Lightweight implementation of AES for resource constrained environment

  • 期刊论文

  • 发表日期：

    2025年3月4日

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  • R. Parthasarathy,
  • P. Saravanan,
  • S. Rajesh Srivatsav,
  • C. M. Manisha

摘要

In order to enhance the data confidentiality and integrity in resource-constrained environments, an optimized hardware implementation of the Advanced Encryption Standard is proposed. An iterative architecture common for both AES-128 encryption and decryption, involving minimum hardware resources, is developed. The sub bytes and inverse sub bytes operations are realized using composite field arithmetic S-box and its inverse, respectively. The matrix constants of the inverse mixcolumns operation of decryption are expressed involving matrix constants of the mixcolumns operation of encryption. Hence, a common equation for both encryption and decryption is derived. Depending upon the requirement, encryption or decryption will be implemented with the minimum resources with appropriate control signals. The proposed work is implemented in both FPGA devices and ASIC platforms. The area occupied by the proposed architecture is 205 slices in the Virtex-5 FPGA device. The area estimate of the proposed design using 180nm technology SCL libraries is only 5644 GE, which highlights the design as a compact implementation of the AES-128 cipher and an optimal choice to ensure the safety of IoT devices.