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<p>To improve the received signal strength beams are formed by multi-element arrays. These beams are focused on the direction of arriving signals, with an intention of maximizing the received signal power. The signals with noise and interference arrived from a distinct direction will be estimated by Uniform Linear Array (ULA) with 10 antenna elements. The earlier signal will be phase-shifted with the help of phase shift beamformer. The Coordinate Rotation Digital Computer (CORDIC) algorithm is used compute the vector angle in signal cluster. The CORDIC algorithm is employed determint the phase shift and frequency offset. The beamformer assumes that incoming signal are narrow banded, a phase shift can estimate the required delay and preserve the incoming signal strength. The beamformer circuit is designed in Xilinx Vivado for simulation and synthesized using both Virtex-7 device and their results are compared with exisiting methods, which is evidence that the proposed design is formidable pertaining to power and delay. This design can operate at 100&#xa0;MHZ with total on-chip power consumption of 725&#xa0;mW.</p>

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Fpga implementation of an efficient phase shift beamformer for narrow band sub-GHz applications

  • 期刊论文

  • 发表日期：

    2025年1月20日

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  • P. Jeyakumar,
  • K. Sudhakar,
  • P. Thanapal,
  • C. Navaneethan,
  • S. Meenatchi

摘要

To improve the received signal strength beams are formed by multi-element arrays. These beams are focused on the direction of arriving signals, with an intention of maximizing the received signal power. The signals with noise and interference arrived from a distinct direction will be estimated by Uniform Linear Array (ULA) with 10 antenna elements. The earlier signal will be phase-shifted with the help of phase shift beamformer. The Coordinate Rotation Digital Computer (CORDIC) algorithm is used compute the vector angle in signal cluster. The CORDIC algorithm is employed determint the phase shift and frequency offset. The beamformer assumes that incoming signal are narrow banded, a phase shift can estimate the required delay and preserve the incoming signal strength. The beamformer circuit is designed in Xilinx Vivado for simulation and synthesized using both Virtex-7 device and their results are compared with exisiting methods, which is evidence that the proposed design is formidable pertaining to power and delay. This design can operate at 100 MHZ with total on-chip power consumption of 725 mW.