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<p>The sparse matrix–vector multiplication (<span>SpMV</span>) kernel is a key kernel in scientific and engineering applications, forming the core of many iterative solvers for linear systems and eigenvalue problems. Due to its low arithmetic intensity and irregular memory access patterns, <span>SpMV</span> remains memory-bound on modern architectures, making its efficient implementation particularly challenging. This paper presents vectorized <span>SpMV</span> routines for RISC-V processors with SIMD support, exploiting the RISC-V Vector Extension (RVV 1.0). We implement and evaluate three storage formats—CSR (Compressed Sparse Row), SELL-<i>p</i> (a vector-friendly variant of ELLPACK), and JDS (Jagged Diagonal Storage)—providing low-level implementations that leverage RVV intrinsics. Performance is assessed on two commercial RISC-V platforms (CanMV-K230 and BananaPi F3) with 128-bit and 256-bit vector registers, and on the EPAC research system featuring 16,384-bit vectors. Results show that the vectorized routines significantly outperform scalar baselines, achieving a variety of speed-ups depending on the format and architecture. These findings highlight the potential of open RISC-V architectures for high-performance sparse linear algebra and provide a foundation for future vector-aware sparse kernel optimizations.</p>

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Sparse matrix–vector product on RISC-V processors with SIMD units

  • 期刊论文

  • 出版模式：

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  • 发表日期：

    2026年4月13日

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  • Andrés E. Tomás,
  • Héctor Martínez,
  • Sandra Catalán,
  • Patricia Siwinska,
  • Adrián Castelló,
  • Marc Casas,
  • Enrique S. Quintana-Ortí

摘要

The sparse matrix–vector multiplication (SpMV) kernel is a key kernel in scientific and engineering applications, forming the core of many iterative solvers for linear systems and eigenvalue problems. Due to its low arithmetic intensity and irregular memory access patterns, SpMV remains memory-bound on modern architectures, making its efficient implementation particularly challenging. This paper presents vectorized SpMV routines for RISC-V processors with SIMD support, exploiting the RISC-V Vector Extension (RVV 1.0). We implement and evaluate three storage formats—CSR (Compressed Sparse Row), SELL-p (a vector-friendly variant of ELLPACK), and JDS (Jagged Diagonal Storage)—providing low-level implementations that leverage RVV intrinsics. Performance is assessed on two commercial RISC-V platforms (CanMV-K230 and BananaPi F3) with 128-bit and 256-bit vector registers, and on the EPAC research system featuring 16,384-bit vectors. Results show that the vectorized routines significantly outperform scalar baselines, achieving a variety of speed-ups depending on the format and architecture. These findings highlight the potential of open RISC-V architectures for high-performance sparse linear algebra and provide a foundation for future vector-aware sparse kernel optimizations.