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<p>Scaling down MOSFETs into the nanometer regime has intensified short-channel effects (SCEs), increased leakage currents, and degraded gate control, limiting the performance and energy efficiency of traditional bulk devices. FinFETs have emerged as a promising alternative due to their superior electrostatic control and scalability. This work presents a comparative analysis of fully depleted SOI FinFETs employing single (Air, SiO<sub>2</sub>, HfO<sub>2</sub>) and dual (HfO<sub>2</sub> + SiO<sub>2</sub>) dielectric spacers across doping concentrations of 1 × 10<sup>17</sup>, 1 × 10<sup>18</sup>, and 1 × 10<sup>19</sup> cm<sup>−3</sup>. The results show that dual dielectric spacers yield up to 35% lower DIBL and 22% improved subthreshold swing over single spacers at aggressive scaling, enabling better leakage suppression and gate control. Simulation results show that dual dielectric spacers significantly suppress leakage and SCEs, while single dielectrics provide better circuit-level performance. The findings offer valuable insights for designing low-power, high-performance nanoscale CMOS devices used in wireless transmission systems, including IoT nodes, RF front-ends, and future 5G/6G applications.</p>

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Dual spacer-engineered FinFETs with enhanced electrostatic control at nanoscale

  • 期刊论文

  • 发表日期：

    2025年8月14日

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  • Md Ilyas Ahmed,
  • A. Niranjil Kumar,
  • B. Lakshmi Prasanna,
  • Asisa Kumar Panigrahy

摘要

Scaling down MOSFETs into the nanometer regime has intensified short-channel effects (SCEs), increased leakage currents, and degraded gate control, limiting the performance and energy efficiency of traditional bulk devices. FinFETs have emerged as a promising alternative due to their superior electrostatic control and scalability. This work presents a comparative analysis of fully depleted SOI FinFETs employing single (Air, SiO2, HfO2) and dual (HfO2 + SiO2) dielectric spacers across doping concentrations of 1 × 1017, 1 × 1018, and 1 × 1019 cm−3. The results show that dual dielectric spacers yield up to 35% lower DIBL and 22% improved subthreshold swing over single spacers at aggressive scaling, enabling better leakage suppression and gate control. Simulation results show that dual dielectric spacers significantly suppress leakage and SCEs, while single dielectrics provide better circuit-level performance. The findings offer valuable insights for designing low-power, high-performance nanoscale CMOS devices used in wireless transmission systems, including IoT nodes, RF front-ends, and future 5G/6G applications.