Energy-efficient SOI FET design with enhanced switching speed and area optimization
摘要
Circular and vertical design approaches are introduced in this study to improve the performance metrics of a double-gate MOS device. The suggested device employs silicon-on-insulator (SOI) technology with active double gates to reduce parasitic operation in digital circuits. Hafnium Oxide (HfO2) is the preferred gate oxide layer over silicon dioxide (SiO2) for improved leakage performance. The transistor only takes cross-sectional area up a total of 706.86 nm2, and the device has a very small radius of only 15 nm. The transistor’s threshold voltage (Vt) is 0.2 V, and its DIBL is 64 mV/V. With an ION/IOFF Ratio of 5 × 104, an ON current of 100 × 10−6 A, and an extremely low OFF current of 2 × 10−9 A are produced. This MOSFET has a respectable Sub-threshold Swing (SS) of 67 mV/Decade and uses a meagre 1.04 × 10−21 J of dynamic power and 0.52 × 10−21 J of static power. The creation of this device will revolutionise the semiconductor industry by making it a strong contender for high-performance, sub-nm power-efficient switching applications.