<p>This study evaluates the performance of a novel Source Pocket Heterojunction Vertical Non-Uniform Channel Double Gate Tunnel Field-Effect Transistor (SP-HJ-VNUCDG-TFET), with and without a hetero gate dielectric. The heterojunction is strategically engineered by integrating GaSb material in the source region and silicon in the channel. This material configuration is specifically aimed at reducing the tunneling width, thereby enhancing the ON-current of the device. To further optimize device performance, a source pocket is incorporated, which significantly improves the subthreshold characteristics. The device performance with varying temperature is systematically analyzed through various key DC and analog parameters, including subthreshold swing (SS), ON-current (I<sub>ON</sub>​), OFF-current (I<sub>OFF</sub>​), threshold voltage (V<sub>T</sub>​), and the I<sub>ON</sub>​/I<sub>OFF</sub>​ ratio, g<sub>m</sub>, f<sub>T</sub>, GBP, TFP, tτ. A detailed comparative study reveals that the proposed device, which employs a hetero gate dielectric, demonstrates superior performance and less sensitive to thermal variations over its counterpart without the hetero gate dielectric (SP-HJ-VNUCDG-TFET). This enhancement is attributed to the improved electrostatic control and reduced gate leakage offered by the hetero gate dielectric. The findings highlight that the proposed device achieves a significant balance between Low energy demand and high operational speed, making it a promising candidate for next-generation low-power, high-performance electronic applications.</p>

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Performance and temperature analysis of pocket-engineered vertical non-uniform channel double-gate TFET with heterojunction and heterodielectric design

  • Swaroop Kumar Macherla,
  • Ekta Goel

摘要

This study evaluates the performance of a novel Source Pocket Heterojunction Vertical Non-Uniform Channel Double Gate Tunnel Field-Effect Transistor (SP-HJ-VNUCDG-TFET), with and without a hetero gate dielectric. The heterojunction is strategically engineered by integrating GaSb material in the source region and silicon in the channel. This material configuration is specifically aimed at reducing the tunneling width, thereby enhancing the ON-current of the device. To further optimize device performance, a source pocket is incorporated, which significantly improves the subthreshold characteristics. The device performance with varying temperature is systematically analyzed through various key DC and analog parameters, including subthreshold swing (SS), ON-current (ION​), OFF-current (IOFF​), threshold voltage (VT​), and the ION​/IOFF​ ratio, gm, fT, GBP, TFP, tτ. A detailed comparative study reveals that the proposed device, which employs a hetero gate dielectric, demonstrates superior performance and less sensitive to thermal variations over its counterpart without the hetero gate dielectric (SP-HJ-VNUCDG-TFET). This enhancement is attributed to the improved electrostatic control and reduced gate leakage offered by the hetero gate dielectric. The findings highlight that the proposed device achieves a significant balance between Low energy demand and high operational speed, making it a promising candidate for next-generation low-power, high-performance electronic applications.