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<p>Hybrid Memory Systems (HMS) balance larger, slower storage (like hard disks) with faster DRAM to efficiently handle data-intensive applications. As the processor-storage gap&#xa0;(commonly known as the ‘memory wall’) grows, prefetching becomes essential for hiding latency. Current sequence-based models are ‘topology-agnostic’, ignoring the specific performance characteristics of different hardware tiers.&#xa0;To address this, we present TAP++, a prefetching framework designed for HMS. TAP++ uses a System-Aware, Tier-Adaptive Transformer (SITA-T) model trained on system-response features to jointly predict future block addresses and determine the optimal destination tier for each prefetch operation. Unlike traditional prefetchers that only predict what data is needed, TAP++ determines where in the hierarchy it should be placed to maximize efficiency. Our evaluation shows TAP++ consistently outperforms state-of-the-art baselines on a wide range of challenging, real-world, and synthetic workloads, increasing the overall cache hit rate by up to 66% and improving the predictive F1 score by up to 18%, with higher hit rates in the faster memory tiers. Additionally, we conduct ablation and sensitivity studies to show the robustness and flexibility of our proposed approach.</p>

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TAP++: a tier-aware transformer for adaptive prefetching system in hybrid memory systems

  • 期刊论文

  • 发表日期：

    2026年2月26日

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  • Chandranil Chakraborttii

摘要

Hybrid Memory Systems (HMS) balance larger, slower storage (like hard disks) with faster DRAM to efficiently handle data-intensive applications. As the processor-storage gap (commonly known as the ‘memory wall’) grows, prefetching becomes essential for hiding latency. Current sequence-based models are ‘topology-agnostic’, ignoring the specific performance characteristics of different hardware tiers. To address this, we present TAP++, a prefetching framework designed for HMS. TAP++ uses a System-Aware, Tier-Adaptive Transformer (SITA-T) model trained on system-response features to jointly predict future block addresses and determine the optimal destination tier for each prefetch operation. Unlike traditional prefetchers that only predict what data is needed, TAP++ determines where in the hierarchy it should be placed to maximize efficiency. Our evaluation shows TAP++ consistently outperforms state-of-the-art baselines on a wide range of challenging, real-world, and synthetic workloads, increasing the overall cache hit rate by up to 66% and improving the predictive F1 score by up to 18%, with higher hit rates in the faster memory tiers. Additionally, we conduct ablation and sensitivity studies to show the robustness and flexibility of our proposed approach.