<p>The efficiency of silicon heterojunction (SHJ) solar cells depends critically on c-Si surface topography and defect passivation. This study optimizes the formation of random pyramids using chemical additives in the texturization solution, achieving pyramids with optimal base and vertex angles and a low surface reflectance of ∼ 10.51%. Interface defect states (D<sub>it</sub>) and surface lifetime (τ<sub>surf</sub>) were analysed at various cell fabrication stages. The deposition of i-a-Si: H layers on both sides of the textured wafer reduced D<sub>it</sub> to ∼ 8.5 × 10<sup>8</sup> eV<sup>− 1</sup>cm<sup>− 2</sup> with τ<sub>surf</sub> ∼ 4.9 ms indicating good chemical passivation of the defects. Adding the carrier-selective layers (p-a-Si: H and n-nc-Si: H) further reduced D<sub>it</sub> to ∼ 7.0 × 10<sup>8</sup> eV<sup>− 1</sup>cm<sup>− 2</sup> and enhanced τ<sub>surf</sub> to ∼ 21.0 ms. However, sputtering-induced plasma damage during ITO deposition increased D<sub>it</sub> to ∼ 11.8 × 10<sup>8</sup> eV<sup>− 1</sup>cm<sup>− 2</sup>, lowering τ<sub>surf</sub> to ∼ 3.3 ms. Optimized c-Si surface conditioning led to a power conversion efficiency of ∼ 22.4% and an open-circuit voltage of ∼ 727 mV from an SHJ cell. Device dark current-voltage analysis also provided insights into the charge carrier recombination dynamics.</p>

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Role of additive-assisted texturing on surface morphology and interface defect density in silicon heterojunction solar cells

  • Honey Sharma,
  • Shrestha Bhattacharya,
  • Shahnawaz Alam,
  • Silajit Manna,
  • Ashutosh Pandey,
  • Son Pal Singh,
  • Vamsi Krishna Komarala

摘要

The efficiency of silicon heterojunction (SHJ) solar cells depends critically on c-Si surface topography and defect passivation. This study optimizes the formation of random pyramids using chemical additives in the texturization solution, achieving pyramids with optimal base and vertex angles and a low surface reflectance of ∼ 10.51%. Interface defect states (Dit) and surface lifetime (τsurf) were analysed at various cell fabrication stages. The deposition of i-a-Si: H layers on both sides of the textured wafer reduced Dit to ∼ 8.5 × 108 eV− 1cm− 2 with τsurf ∼ 4.9 ms indicating good chemical passivation of the defects. Adding the carrier-selective layers (p-a-Si: H and n-nc-Si: H) further reduced Dit to ∼ 7.0 × 108 eV− 1cm− 2 and enhanced τsurf to ∼ 21.0 ms. However, sputtering-induced plasma damage during ITO deposition increased Dit to ∼ 11.8 × 108 eV− 1cm− 2, lowering τsurf to ∼ 3.3 ms. Optimized c-Si surface conditioning led to a power conversion efficiency of ∼ 22.4% and an open-circuit voltage of ∼ 727 mV from an SHJ cell. Device dark current-voltage analysis also provided insights into the charge carrier recombination dynamics.