<p>This work focuses on a new multilevel inverter based on switched-capacitor (SC) units with reduced devices. To generate a 13-level output with a voltage gain of six, the proposed topology utilizes fourteen switches, zero floating diodes, three capacitors, and only a single DC source. The distinguished feature of the offered inverter is its ability to provide simultaneously high voltage gain and a low-cost function. Furthermore, by eliminating the back-end H-bridge unit, the maximum blocking voltage is restricted to half of the maximum output voltage, as much as 3<i>V</i><sub>dc</sub>, which leads to diminishing the switches’ total blocking voltage. Because of the use of multiple half-bridge modules, four pairs of switches are logically complementary to each other, thus reducing the required number of gate drivers. All capacitors employed in the SC units are charged four times in the fundamental cycle, maintaining their voltage ripple within the authorized limit. Moreover, through a simplified switching technique, such as the nearest-level control scheme, the capacitors can act self-balanced without requiring a voltage sensor or any additional intricate circuits. The simulations and experimental results, conducted using the MATLAB platform and Arduino Due based on ARM-Cortex core, respectively, confirm the accuracy of the performance of the proposed topology, both in steady-state and transient responses.</p>

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A novel 13-level single DC source inverter based on switched-capacitor units with high voltage gain and low-cost function

  • Seyed Jafar Salehi,
  • Mohammad Ali Shamsi-Nejad

摘要

This work focuses on a new multilevel inverter based on switched-capacitor (SC) units with reduced devices. To generate a 13-level output with a voltage gain of six, the proposed topology utilizes fourteen switches, zero floating diodes, three capacitors, and only a single DC source. The distinguished feature of the offered inverter is its ability to provide simultaneously high voltage gain and a low-cost function. Furthermore, by eliminating the back-end H-bridge unit, the maximum blocking voltage is restricted to half of the maximum output voltage, as much as 3Vdc, which leads to diminishing the switches’ total blocking voltage. Because of the use of multiple half-bridge modules, four pairs of switches are logically complementary to each other, thus reducing the required number of gate drivers. All capacitors employed in the SC units are charged four times in the fundamental cycle, maintaining their voltage ripple within the authorized limit. Moreover, through a simplified switching technique, such as the nearest-level control scheme, the capacitors can act self-balanced without requiring a voltage sensor or any additional intricate circuits. The simulations and experimental results, conducted using the MATLAB platform and Arduino Due based on ARM-Cortex core, respectively, confirm the accuracy of the performance of the proposed topology, both in steady-state and transient responses.