High-efficiency nine-level inverter using switched-capacitor technique with optimized switch count
摘要
Switched-capacitor multilevel inverters (SCMLIs) have garnered significant attention due to their ability to generate multiple voltage levels with fewer components and high efficiency. However, conventional MLIs often suffer from high switch count, complex control schemes, and challenges in balancing the DC-link capacitors. This paper proposes a novel nine-level SCMLI non-boosting topology that addresses these limitations through a reduced switch architecture with inherent voltage self-balancing. The topology achieves a nine-level output using only eight switches, two DC sources, and two capacitors, eliminating the need for auxiliary balancing circuits. The results confirm a low total harmonic distortion (THD) of 0.85%, an inverter efficiency of 98.6%, and the maximum blocking voltage of each switch combined has a value of 5.5