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<p>In this paper, the detailed physical insight towards understanding isothermal and electrothermal snapback current–voltage characteristics of n-FET-based electrostatic discharge (ESD) protection devices (like gate-grounded NMOS (GG-NMOS)) is investigated under ultra-high-current pulsing or ESD conditions. Under such conditions, the charge movement in different regions of the device structure and their mutual electrostatic coupling has been clearly understood through a two-dimensional technology computer-aided design (TCAD) device simulation results, which provide predictive analytical model of snapback current–voltage (<i>I-V</i>) characteristics. Further, the process of parasitic bipolar activities in the proposed device structure has been discussed to describe terminal characteristics. The effect on the electrical characteristics due to physical parameters variation such as gate length (<i>L</i><sub>g</sub>), substrate doping (<i>P</i><sub>Sub</sub>), source/drain doping (<i>N</i><sub>S</sub>/<i>N</i><sub>D</sub>) is investigated through detailed parametric analysis. Further, transient device simulations are performed on 180-nm GG-NMOS at a specified drain current pulse of <i>1A/ns</i> at different temperature ranges from 25 to 125&#xa0;℃. The effects of transient high current injections on the GG-NMOS are examined in terms of <i>I–V</i> characteristics and ESD failure models through isothermal and electrothermal behaviour.</p>

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Isothermal and electrothermal characteristics of GG-NMOS for ESD applications: design and analysis

  • 期刊论文

  • 发表日期：

    2025年6月5日

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  • Prabhat Kumar,
  • Anant Kumar,
  • Dheeraj Kumar Sinha,
  • Sanjay Kumar

摘要

In this paper, the detailed physical insight towards understanding isothermal and electrothermal snapback current–voltage characteristics of n-FET-based electrostatic discharge (ESD) protection devices (like gate-grounded NMOS (GG-NMOS)) is investigated under ultra-high-current pulsing or ESD conditions. Under such conditions, the charge movement in different regions of the device structure and their mutual electrostatic coupling has been clearly understood through a two-dimensional technology computer-aided design (TCAD) device simulation results, which provide predictive analytical model of snapback current–voltage (I-V) characteristics. Further, the process of parasitic bipolar activities in the proposed device structure has been discussed to describe terminal characteristics. The effect on the electrical characteristics due to physical parameters variation such as gate length (Lg), substrate doping (PSub), source/drain doping (NS/ND) is investigated through detailed parametric analysis. Further, transient device simulations are performed on 180-nm GG-NMOS at a specified drain current pulse of 1A/ns at different temperature ranges from 25 to 125 ℃. The effects of transient high current injections on the GG-NMOS are examined in terms of I–V characteristics and ESD failure models through isothermal and electrothermal behaviour.