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<p>In advanced semiconductor manufacturing, copper interconnects fabricated via the dual damascene process rely heavily on chemical mechanical planarization (CMP) to achieve global planarity and defect-free surfaces. However, achieving optimal material removal uniformity, minimal dishing in recessed features, and low surface roughness remains challenging for through-silicon via (TSV) copper structures on patterned wafers. To address these issues, this study developed a novel quasi-static downforce simulation apparatus combined with the quadrat method for asperity spatial analysis to elucidate the role of polishing pad layer architecture in CMP performance. Multi-scale nano-indentation and real-time contact imaging were employed to compare the monolithic IC1000 polishing pad with the bilayer ICSU polishing pad. Results revealed that the ICSU polishing pad, owing to its compliant Suba™ IV sub-layer, exhibits greater asperity deformability, higher real contact area ratio (approximately 8–12% greater than that of the IC1000 pad), and more uniform asperity distribution under various downforces (1–3 Psi). Consequently, the ICSU polishing pad delivered superior CMP surface roughness (Sa of approximately 0.8&#xa0;nm) and within-wafer non-uniformity (WIWNU 15–20% lower than that of the IC1000 pad) across the tested downforce range. Regarding dishing, the bilayer ICSU pad exhibited comparable or slightly better performance at lower downforces (1–2 Psi), while the monolithic IC1000 pad provided superior dishing control at the higher downforce of 3 Psi (dishing depth reduced by approximately 4–6&#xa0;nm). These findings highlight fundamental trade-offs in polishing pad design and offer practical guidance for polishing pad selection in high-density copper interconnect CMP processes. The results, obtained on 2-inch test wafers, are most applicable to low-to-moderate pressure CMP of TSV and dual-damascene structures when scaled to industrial conditions.</p>

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Study on the effect of polishing pad layer structure on dishing control in chemical mechanical planarization of through-silicon via copper patterned wafer

  • 期刊论文

  • 发表日期：

    2026年5月2日

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  • Quoc-Phong Pham,
  • Le Nam Quoc Huy

摘要

In advanced semiconductor manufacturing, copper interconnects fabricated via the dual damascene process rely heavily on chemical mechanical planarization (CMP) to achieve global planarity and defect-free surfaces. However, achieving optimal material removal uniformity, minimal dishing in recessed features, and low surface roughness remains challenging for through-silicon via (TSV) copper structures on patterned wafers. To address these issues, this study developed a novel quasi-static downforce simulation apparatus combined with the quadrat method for asperity spatial analysis to elucidate the role of polishing pad layer architecture in CMP performance. Multi-scale nano-indentation and real-time contact imaging were employed to compare the monolithic IC1000 polishing pad with the bilayer ICSU polishing pad. Results revealed that the ICSU polishing pad, owing to its compliant Suba™ IV sub-layer, exhibits greater asperity deformability, higher real contact area ratio (approximately 8–12% greater than that of the IC1000 pad), and more uniform asperity distribution under various downforces (1–3 Psi). Consequently, the ICSU polishing pad delivered superior CMP surface roughness (Sa of approximately 0.8 nm) and within-wafer non-uniformity (WIWNU 15–20% lower than that of the IC1000 pad) across the tested downforce range. Regarding dishing, the bilayer ICSU pad exhibited comparable or slightly better performance at lower downforces (1–2 Psi), while the monolithic IC1000 pad provided superior dishing control at the higher downforce of 3 Psi (dishing depth reduced by approximately 4–6 nm). These findings highlight fundamental trade-offs in polishing pad design and offer practical guidance for polishing pad selection in high-density copper interconnect CMP processes. The results, obtained on 2-inch test wafers, are most applicable to low-to-moderate pressure CMP of TSV and dual-damascene structures when scaled to industrial conditions.