Scholarlink

<p>Silicon wafers form the foundation of modern-day electronics and solar technologies and are subjected to immense thermal stresses during advanced packaging processes, which in turn manifest as warpage to eventually compromise device reliability. The present paper targets a study on the warpage behavior of silicon oxide-coated wafers with diameters of 4-inch, 6-inch, and 8-inch and respective thickness of 525&#xa0;μm, 675&#xa0;μm, and 725&#xa0;μm under a thermal profile that reaches up to 268&#xa0;°C. Experiments were conducted to measure warpage via a laser displacement sensor indicating increased warpage with increased wafer size: 0.3&#xa0;mm for 4-inch, 0.6&#xa0;mm for 6-inch, and 0.9&#xa0;mm for 8-inch wafers. In addition, five different machine learning algorithms are evaluated to model and predict warpage, among which the Random Forest model exhibited superior performance. Optimization of the RF model using k-fold validation, shape factor analysis, and heat map evaluation showed high predictive accuracy with a low mean error at R² = 0.95. Further validation was done with experimental data, and extrapolation was done for a 12-inch wafer, showing consistent deformation trends. Comparative analysis was performed between ML predictions and ANSYS simulations, revealing that the ML approach yields a much lower error percentage in a range of 5–10% compared to ANSYS (10–20%), thus emphasizing the computational efficiency and predictive precision of ML-based modeling. This approach of hybrid experimentation and ML presents a scalable and cost-effective solution to solve warpage-related issues in semiconductor manufacturing and electronics packaging.</p>

错误：搜索内容不能为空，请输入英文关键词
错误：关键词超出字数限制，请精简
高级检索

Semiconductor wafer warpage in electronics packaging: a hybrid investigation with ML and experimental insights

  • 期刊论文

  • 发表日期：

    2025年12月20日

查看全文
  • Krishnamoorthy Ramalingam,
  • Mohd. Zulkifly Abdullah,
  • Mohamad Aizat Abas,
  • Kok Hwa Yu,
  • Roslan Kamarudin,
  • Muhammad Razi Abdul Rahman,
  • Shaw Fong Wong,
  • Pooi Kit Lam,
  • Bok Eng Cheah

摘要

Silicon wafers form the foundation of modern-day electronics and solar technologies and are subjected to immense thermal stresses during advanced packaging processes, which in turn manifest as warpage to eventually compromise device reliability. The present paper targets a study on the warpage behavior of silicon oxide-coated wafers with diameters of 4-inch, 6-inch, and 8-inch and respective thickness of 525 μm, 675 μm, and 725 μm under a thermal profile that reaches up to 268 °C. Experiments were conducted to measure warpage via a laser displacement sensor indicating increased warpage with increased wafer size: 0.3 mm for 4-inch, 0.6 mm for 6-inch, and 0.9 mm for 8-inch wafers. In addition, five different machine learning algorithms are evaluated to model and predict warpage, among which the Random Forest model exhibited superior performance. Optimization of the RF model using k-fold validation, shape factor analysis, and heat map evaluation showed high predictive accuracy with a low mean error at R² = 0.95. Further validation was done with experimental data, and extrapolation was done for a 12-inch wafer, showing consistent deformation trends. Comparative analysis was performed between ML predictions and ANSYS simulations, revealing that the ML approach yields a much lower error percentage in a range of 5–10% compared to ANSYS (10–20%), thus emphasizing the computational efficiency and predictive precision of ML-based modeling. This approach of hybrid experimentation and ML presents a scalable and cost-effective solution to solve warpage-related issues in semiconductor manufacturing and electronics packaging.