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<p>The analog Computing-in-Memory (CIM) architecture used in smart sensing systems offers significant advantages in terms of integration, energy efficiency, and throughput. However, high-precision and high-computational analog CIM systems require high-resolution analog-to-digital converters (ADCs) for quantization, which consume a significant amount of power and occupy a large portion of layout area resources. To break this dilemma, this paper proposes a capacitor-sharing ADC (CS-ADC) for charge-domain CIM architecture. The CS-ADC utilizes part of the capacitors within the CIM units as the Capacitor Digital-to-Analog Converter (CDAC) within the ADC, the rest as the dynamic range calibration capacitors of the ADC. On the one hand, the power consumption decreases due to the charge averaging of the Multiply-Accumulate (MAC) operation in the CIM array merged with the process of ADC sampling. On the other hand, the area decreases due to the multiplexing of capacitors. Furthermore, the CS-ADC features reconfigurable resolution to enhance system scalability. This architectural fusion demonstrates its efficiency through absolute metrics: it restricts the physical ADC area overhead to a mere 4.35% of the entire CS-CIM macro and achieves a Walden Figure-of-Merit (FoM) of 2.11 fJ/conversion-step in 8-bit mode, effectively addressing the severe area and power bottlenecks in edge AI applications.</p>

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CS-ADC: A Capacitor-Sharing ADC with Reconfigurable Resolution in Charge-Domain Computing-in-Memory for Smart Sensing Applications

  • 期刊论文

  • 发表日期：

    2026年7月14日

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  • Tianyu Liu,
  • Erxiang Ren,
  • Guilin Zhu,
  • Li Luo,
  • Fei Qiao,
  • Bo Liu

摘要

The analog Computing-in-Memory (CIM) architecture used in smart sensing systems offers significant advantages in terms of integration, energy efficiency, and throughput. However, high-precision and high-computational analog CIM systems require high-resolution analog-to-digital converters (ADCs) for quantization, which consume a significant amount of power and occupy a large portion of layout area resources. To break this dilemma, this paper proposes a capacitor-sharing ADC (CS-ADC) for charge-domain CIM architecture. The CS-ADC utilizes part of the capacitors within the CIM units as the Capacitor Digital-to-Analog Converter (CDAC) within the ADC, the rest as the dynamic range calibration capacitors of the ADC. On the one hand, the power consumption decreases due to the charge averaging of the Multiply-Accumulate (MAC) operation in the CIM array merged with the process of ADC sampling. On the other hand, the area decreases due to the multiplexing of capacitors. Furthermore, the CS-ADC features reconfigurable resolution to enhance system scalability. This architectural fusion demonstrates its efficiency through absolute metrics: it restricts the physical ADC area overhead to a mere 4.35% of the entire CS-CIM macro and achieves a Walden Figure-of-Merit (FoM) of 2.11 fJ/conversion-step in 8-bit mode, effectively addressing the severe area and power bottlenecks in edge AI applications.