<p>The main challenges faced with pseudo-random number generation using binary logic based Linear feedback shift register (LFSR) are limited state density, higher clock power consumption, and large interconnection overhead. Multi-valued logic (MVL) design is one of the possible solutions that provides the benefits of improved computational efficiency, reduced clock power consumption and reduced interconnect area for the realization of linear feedback shift registers. Hence, this work presents pseudo-random number generation using a ternary logic linear feedback shift register. Accordingly, two ternary D-flip-flop designs integrated with reset capability are introduced. The first one is realized using positive/negative multiplexers and a power optimized Standard ternary buffer (STB). The second D-flip-flop is realized using shifting literals and STB design, employing maste-slave architecture. Further, these D-flip flops are arranged with appropriate taps, and module-3 adder is applied in the feedback path to construct multi-stage linear feedback shift-register structures. All ternary circuits harness the variable threshold characteristic of Carbon nanotube field-effect transistors for implementation. The performance analysis of the proposed shift register designs is carried out using the 32nm-CNTFET Stanford model with HSPICE software. The simulation results show that the proposed 4-bit LFSR design reveals an improvement in power consumption of more than 80% compared with other state-of-the-art counterparts. Moreover, minor deviations in power and energy consumption are obtained for the proposed designs when tested under different process variation conditions. These findings demonstrate that the proposed ternary LFSR provides an energy-efficient, high density state-space and scalable solution for pseudo-random number generation in applications such as low-power cryptographic systems, hardware security primitives (PUFs), and built-in self-test (BIST) for next-generation digital circuits.</p>