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<p>Time-to-digital converters (TDCs) are widely utilized in all-digital phase-locked loops. However, linear operation of high-resolution TDCs often incurs substantial area overhead or a significantly increased circuit complexity. This work presents a high-linearity time-to-digital converter based on resistive random access memory (RRAM). Fine-tuning of the delay elements within the Vernier delay line is achieved by tuning the resistance of RRAM, thereby significantly enhancing the linearity of the TDC. The proposed architecture is implemented in a 180-nm CMOS process. Results indicate an effective resolution of 3.03&#xa0;ps and a differential nonlinearity (DNL) of 0.013&#xa0;LSB. Moreover, the TDC maintains high linearity even despite intrinsic RRAM resistance variability, with DNL remaining below 0.15&#xa0;LSB.</p>

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A 0.013 DNL, 3 ps Resolution Vernier Time-to-Digital Converter Using 3-D Resistive Random Access Memory

  • 期刊论文

  • 发表日期：

    2026年5月18日

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  • Rongjian Wu,
  • Helong Lu,
  • Dengyun Lei,
  • Feng Zhang,
  • Lei Wu,
  • Yuan Liu

摘要

Time-to-digital converters (TDCs) are widely utilized in all-digital phase-locked loops. However, linear operation of high-resolution TDCs often incurs substantial area overhead or a significantly increased circuit complexity. This work presents a high-linearity time-to-digital converter based on resistive random access memory (RRAM). Fine-tuning of the delay elements within the Vernier delay line is achieved by tuning the resistance of RRAM, thereby significantly enhancing the linearity of the TDC. The proposed architecture is implemented in a 180-nm CMOS process. Results indicate an effective resolution of 3.03 ps and a differential nonlinearity (DNL) of 0.013 LSB. Moreover, the TDC maintains high linearity even despite intrinsic RRAM resistance variability, with DNL remaining below 0.15 LSB.