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<p>A single-channel 200-MS/s 14-bit successive-approximation-register (SAR) analog-to-digital converter (ADC) is presented. To enhance the ADC accuracy and speed, three key techniques are adopted. Firstly, a coarse-fine architecture is utilized to increase settling time of MSB capacitor in the fine DAC equivalently. A unified bootstrap circuit shared by both the coarse and fine sampling networks is also employed to minimize timing skew between two sampling networks, reducing sampling mismatch error. Secondly, an inverter-based hybrid-mode pre-amplifier accelerates large-signal recovery while suppressing kickback noise in small-signal conditions, improving both speed and dynamic linearity. Thirdly, a replica-bias-based common-mode feedback (CMFB) scheme employs active common-mode regulation to stabilize the inverter-based pre-amplifier, addressing its sensitivity to input common-mode voltage as well as process, voltage, and temperature (PVT) variations. At <InlineEquation ID="IEq1"> <EquationSource Format="TEX">\(\text {1V}_\text {pp,diff}\)</EquationSource> <EquationSource Format="MATHML"><math> <msub> <mtext>1V</mtext> <mtext>pp,diff</mtext> </msub> </math></EquationSource> </InlineEquation> input amplitude, the fabricated 28-nm CMOS prototype ADC achieves a SNDR of 65.3 dB, a SFDR of 85.2 dB at the Nyquist input. The ADC core occupies an area of 0.06 <InlineEquation ID="IEq2"> <EquationSource Format="TEX">\(\text {mm}^{\text {2}}\)</EquationSource> <EquationSource Format="MATHML"><math> <msup> <mtext>mm</mtext> <mtext>2</mtext> </msup> </math></EquationSource> </InlineEquation> and consumes 16.4 mW under the 1-V power supply, yielding a Schreier FoM of 163.2 dB.</p>

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A 14-b 65.3-dB SNDR 200-MS/s Coarse-fine SAR ADC with Rail-to-Rail Input Common Mode Range in 28-nm CMOS

  • 期刊论文

  • 发表日期：

    2026年5月11日

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  • Jiangfan Wen,
  • Hui Hu,
  • Hui Zhang,
  • Bingbing Yao,
  • Lei Qiu

摘要

A single-channel 200-MS/s 14-bit successive-approximation-register (SAR) analog-to-digital converter (ADC) is presented. To enhance the ADC accuracy and speed, three key techniques are adopted. Firstly, a coarse-fine architecture is utilized to increase settling time of MSB capacitor in the fine DAC equivalently. A unified bootstrap circuit shared by both the coarse and fine sampling networks is also employed to minimize timing skew between two sampling networks, reducing sampling mismatch error. Secondly, an inverter-based hybrid-mode pre-amplifier accelerates large-signal recovery while suppressing kickback noise in small-signal conditions, improving both speed and dynamic linearity. Thirdly, a replica-bias-based common-mode feedback (CMFB) scheme employs active common-mode regulation to stabilize the inverter-based pre-amplifier, addressing its sensitivity to input common-mode voltage as well as process, voltage, and temperature (PVT) variations. At \(\text {1V}_\text {pp,diff}\) 1V pp,diff input amplitude, the fabricated 28-nm CMOS prototype ADC achieves a SNDR of 65.3 dB, a SFDR of 85.2 dB at the Nyquist input. The ADC core occupies an area of 0.06 \(\text {mm}^{\text {2}}\) mm 2 and consumes 16.4 mW under the 1-V power supply, yielding a Schreier FoM of 163.2 dB.