Scholarlink

<p>This paper presents a compactly designed <i>Ka</i>-band low-noise amplifier (LNA) fabricated in a 65-nm CMOS process. A differential common-source topology is adopted as amplifier-stages, while transformer-based networks are employed to achieve gain matching and noise optimization. Bandwidth (<i>BW</i>) extension is further realized through merged inductive peaking, which effectively improved the circuit’s high-frequency response. The fabricated chip occupies a compact core area of 0.18 × 0.38 mm<sup>2</sup> and is characterized using on-wafer probing with PCB-based biasing. Measurement results show that the proposed LNA achieves a peak gain of 16.6&#xa0;dB with 3-dB <i>BW</i> from 22.8 to 34&#xa0;GHz, a minimum noise figure (<i>NF</i>) of 3.6&#xa0;dB, and power consumption (<i>P</i><sub><i>DC</i></sub>) of 23 mW from a 1-V supply. The results are in good agreement with simulations and validate the effectiveness of the design methodology. Compared with state-of-the-art compact CMOS LNAs in similar frequency band, this design offers competitive overall performance based on an ultra-compact core chip size. It can be a strong candidate for 5G, satellite communication, and phased-array receiver front-ends.</p>

错误：搜索内容不能为空，请输入英文关键词
错误：关键词超出字数限制，请精简
高级检索

A Compact Differential CMOS LNA for 5G mm-Wave Receiver Front-Ends

  • 期刊论文

  • 发表日期：

    2026年4月29日

查看全文
  • Bingfei Dou,
  • Huimin Fan,
  • Jinzhong Sun,
  • Jiabing Zhu,
  • Xiaojing Yao

摘要

This paper presents a compactly designed Ka-band low-noise amplifier (LNA) fabricated in a 65-nm CMOS process. A differential common-source topology is adopted as amplifier-stages, while transformer-based networks are employed to achieve gain matching and noise optimization. Bandwidth (BW) extension is further realized through merged inductive peaking, which effectively improved the circuit’s high-frequency response. The fabricated chip occupies a compact core area of 0.18 × 0.38 mm2 and is characterized using on-wafer probing with PCB-based biasing. Measurement results show that the proposed LNA achieves a peak gain of 16.6 dB with 3-dB BW from 22.8 to 34 GHz, a minimum noise figure (NF) of 3.6 dB, and power consumption (PDC) of 23 mW from a 1-V supply. The results are in good agreement with simulations and validate the effectiveness of the design methodology. Compared with state-of-the-art compact CMOS LNAs in similar frequency band, this design offers competitive overall performance based on an ultra-compact core chip size. It can be a strong candidate for 5G, satellite communication, and phased-array receiver front-ends.