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<p>Successive approximation register analog to digital converters (SAR ADCs) are a type of ADCs with low power consumption, simple structure, and reliable performance. They offer a wide range of options in terms of precision and sampling rate, thus being widely used in various integrated circuits. In high precision scenarios, traditional SAR ADCs often face issues of linearity degradation caused by capacitor mismatch and comparator noise. To address these problems, this work proposes a 5-MS/s 16-bit least mean square (LMS) calibration SAR ADC based on a hybrid offset storage comparator. This SAR ADC adopts two key technologies: (1) A multi-stage hybrid offset storage comparator structure is designed, which effectively reduces comparator offset and noise while improving comparison speed; (2) The LMS algorithm is combined with dynamic noise balancing technology to achieve adaptive calibration of capacitor digital to analog converter (CDAC) mismatch, significantly enhancing the precision of the SAR ADC. Experimental results show that at sampling rate of 5-MS/s, the ADC achieves signal to noise and distortion ratio (SNDR) of 95.5&#xa0;dB, a spurious free dynamic range (SFDR) of 103.7&#xa0;dB, with the SNDR improved by 23&#xa0;dB after calibration. The core power consumption is 12.1 mW, and the effective area is 0.96 mm<sup>2</sup>.</p>

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A 5-MS/s 16-Bit LMS Calibration SAR ADC Based on a Hybrid Offset Storage Comparator

  • 期刊论文

  • 发表日期：

    2026年4月11日

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  • Wei Hu,
  • Quan Li,
  • Nuo Chen,
  • Bin Liang,
  • Haowen Tu,
  • Yongqian Du

摘要

Successive approximation register analog to digital converters (SAR ADCs) are a type of ADCs with low power consumption, simple structure, and reliable performance. They offer a wide range of options in terms of precision and sampling rate, thus being widely used in various integrated circuits. In high precision scenarios, traditional SAR ADCs often face issues of linearity degradation caused by capacitor mismatch and comparator noise. To address these problems, this work proposes a 5-MS/s 16-bit least mean square (LMS) calibration SAR ADC based on a hybrid offset storage comparator. This SAR ADC adopts two key technologies: (1) A multi-stage hybrid offset storage comparator structure is designed, which effectively reduces comparator offset and noise while improving comparison speed; (2) The LMS algorithm is combined with dynamic noise balancing technology to achieve adaptive calibration of capacitor digital to analog converter (CDAC) mismatch, significantly enhancing the precision of the SAR ADC. Experimental results show that at sampling rate of 5-MS/s, the ADC achieves signal to noise and distortion ratio (SNDR) of 95.5 dB, a spurious free dynamic range (SFDR) of 103.7 dB, with the SNDR improved by 23 dB after calibration. The core power consumption is 12.1 mW, and the effective area is 0.96 mm2.