A simple reconfigurable decimation architecture is proposed for the latest zero-rotated Cascaded Integrator-Comb filters which were previously limited to even downsampling factors \(R\) . The innovation of this architecture lies in its ability to accommodate factors \(R\) with any parity, thereby providing the desirable reconfigurability feature that was not available in these zero-rotated systems. As a result, they can be applied in emergent multistandard communication systems where adjustability of \(R\) is needed. It is shown that the improvement of worst-case aliasing rejection of these filters remains effective for odd factors \(R\) . Besides, the proposed processing core preserves unaltered the power-aware approach and the hardware utilization trade-offs that zero-rotated even- \(R\) solutions establish to perform the improvement of attenuation. Truncation analysis is detailed to show how to compute the internal bus widths of the architecture, and how to estimate appropriately the implementation costs.
