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<p>Contemporary computing architectures need low power consumption, less area and high-speed processing. The researchers are working on enhanced computation models to meet the demands that emerging technological advancement enforces. Multipliers and Adders are the two most widely used computation blocks in such processors. In this paper, one such multiplier architecture has been proposed. Approximation in results does not affect the quality of result expected out of the processors that work in line with error tolerant mechanisms. Power consumption can be greatly reduced once there is acceptance of error trade-off. Many approximate Multiplier architectures have been proposed that discusses on power and energy reduction based on approximation of result. Logarithmic Multipliers are one such category of approximate multipliers where the multiplication process is converted into addition process. A hybrid combination of truncation scheme and segmentation scheme Approximate Logarithmic Multiplier has been proposed. This architecture was designed, simulated for results, synthesized using 45&#xa0;nm digital library and validated with some error tolerant image processing applications. The parameters considered and compared with other conventional schemes are Power, Delay, Area and Power Delay Product (PDP). Upon comparison and further analysis, it was observed that the PDP of proposed multiplier is decreased by up to 17.25% with Mean Relative Error Distance dropping to 10.91% on par with certain 16-bit conventional multipliers. Also, a better performance was observed when the proposed design incorporated in image processing and Deep learning applications.</p>

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Design and Analysis of A Robust Energy Efficient Approximate Logarithmic (A-REAL) Multiplier for Image and Deep Learning Applications

  • 期刊论文

  • 发表日期：

    2026年3月7日

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  • B. Anishfathima,
  • C. Vasanthanayaki

摘要

Contemporary computing architectures need low power consumption, less area and high-speed processing. The researchers are working on enhanced computation models to meet the demands that emerging technological advancement enforces. Multipliers and Adders are the two most widely used computation blocks in such processors. In this paper, one such multiplier architecture has been proposed. Approximation in results does not affect the quality of result expected out of the processors that work in line with error tolerant mechanisms. Power consumption can be greatly reduced once there is acceptance of error trade-off. Many approximate Multiplier architectures have been proposed that discusses on power and energy reduction based on approximation of result. Logarithmic Multipliers are one such category of approximate multipliers where the multiplication process is converted into addition process. A hybrid combination of truncation scheme and segmentation scheme Approximate Logarithmic Multiplier has been proposed. This architecture was designed, simulated for results, synthesized using 45 nm digital library and validated with some error tolerant image processing applications. The parameters considered and compared with other conventional schemes are Power, Delay, Area and Power Delay Product (PDP). Upon comparison and further analysis, it was observed that the PDP of proposed multiplier is decreased by up to 17.25% with Mean Relative Error Distance dropping to 10.91% on par with certain 16-bit conventional multipliers. Also, a better performance was observed when the proposed design incorporated in image processing and Deep learning applications.