<p>This work proposes a highly efficient compression scheme utilizing a VLSI-based discrete Haar Wavelet transform (DHWT) architecture. This scheme aims to facilitate improved transmission and storage, particularly in resource-constrained environments for electrocardiogram (ECG) signal processing. It presents pruned, approximate and pruned, and truncated DHWT architectures (PDHWT, AxPDHWT, and TDHWT, respectively) up to level 5, targeting ultra-high energy efficiency in ECG data compression. Among the developed solutions, the most energy-efficient and area-optimized approach simultaneously employs all three compression techniques (pruning, approximation, and truncation). The PDHWT technique significantly saves energy by eliminating redundant components in this combined approach. The AxPDHWT approach enhances performance by removing the most computationally expensive elements. Finally, TDHWT reduces the number of input bits, leading to a lower-complexity architecture. The combined techniques achieve a minimum compression ratio (MCR) of 0.03125 (<InlineEquation ID="IEq1"> <EquationSource Format="TEX">$\frac{1}{32}$</EquationSource> <EquationSource Format="MATHML"><math> <mfrac> <mn>1</mn> <mn>32</mn> </mfrac> </math></EquationSource> </InlineEquation>) and a percent root difference (PRD) of less than 2.08. The VLSI architecture implementation leverages 65 nm CMOS technology, with a maximum frequency of 1.10GHz, and a target frequency of 125KHz (for comparison with the results found in the literature). The most power-efficient solution combines all three techniques (truncation, pruning, and approximation), achieving significant power savings. Specifically, the architecture with truncation demonstrates exceptional performance, achieving a compression ratio of <InlineEquation ID="IEq2"> <EquationSource Format="TEX">$\frac{1}{16}$</EquationSource> <EquationSource Format="MATHML"><math> <mfrac> <mn>1</mn> <mn>16</mn> </mfrac> </math></EquationSource> </InlineEquation>, a worst-case accuracy of 0.96, a PRD of 4.41, a total area of 771.20 <InlineEquation ID="IEq3"> <EquationSource Format="TEX">$\mu m^{2}$</EquationSource> <EquationSource Format="MATHML"><math> <mrow> <mi>μ</mi> <msup> <mi>m</mi> <mn>2</mn> </msup> </mrow> </math></EquationSource> </InlineEquation>, and the lowest power consumption of 0.60 <InlineEquation ID="IEq4"> <EquationSource Format="TEX">$\mu W$</EquationSource> <EquationSource Format="MATHML"><math> <mrow> <mi>μ</mi> <mi>W</mi> </mrow> </math></EquationSource> </InlineEquation>.</p>

A Power-Efficient Approximate Multi-Level Discrete Haar Wavelet Transform Design for ECG Data Compression

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2026年4月6日

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Arthur Cardozo,
Morgana M. A. da Rosa,
Henrique Seidel,
Rodrigo Lopes,
Eduardo A. C. da Costa,
Rafael Soares

摘要

This work proposes a highly efficient compression scheme utilizing a VLSI-based discrete Haar Wavelet transform (DHWT) architecture. This scheme aims to facilitate improved transmission and storage, particularly in resource-constrained environments for electrocardiogram (ECG) signal processing. It presents pruned, approximate and pruned, and truncated DHWT architectures (PDHWT, AxPDHWT, and TDHWT, respectively) up to level 5, targeting ultra-high energy efficiency in ECG data compression. Among the developed solutions, the most energy-efficient and area-optimized approach simultaneously employs all three compression techniques (pruning, approximation, and truncation). The PDHWT technique significantly saves energy by eliminating redundant components in this combined approach. The AxPDHWT approach enhances performance by removing the most computationally expensive elements. Finally, TDHWT reduces the number of input bits, leading to a lower-complexity architecture. The combined techniques achieve a minimum compression ratio (MCR) of 0.03125 ( $\frac{1}{32}$ $\frac{1}{32}$ ) and a percent root difference (PRD) of less than 2.08. The VLSI architecture implementation leverages 65 nm CMOS technology, with a maximum frequency of 1.10GHz, and a target frequency of 125KHz (for comparison with the results found in the literature). The most power-efficient solution combines all three techniques (truncation, pruning, and approximation), achieving significant power savings. Specifically, the architecture with truncation demonstrates exceptional performance, achieving a compression ratio of $\frac{1}{16}$ $\frac{1}{16}$ , a worst-case accuracy of 0.96, a PRD of 4.41, a total area of 771.20 $\mu m^{2}$ $μ m^{2}$ , and the lowest power consumption of 0.60 $\mu W$ $μ W$ .