<p>The radix-4 Booth algorithm is a cornerstone in digital multiplier design, yet its conventional implementation using a 3:2 compressor for the single-bit compensation partial product has long been recognized as a bottleneck, impeding the overall performance of multipliers. To address this limitation, this paper introduces an efficient 6-concurrent 4:2 compressor and demonstrates its effectiveness in a radix-4 Booth multiplier by replacing the conventional 3:2-compressor-based reduction logic. The proposed 6-concurrent 4:2 compressor operates in two distinct yet synergistic parts: carry calculation and subsequent reception. Using this compressor, the single-bit compensation partial product can be handled directly in the first-stage compression, thereby eliminating the additional final 3:2-compressor stage required in conventional designs. The proposed compressor design not only refines the conventional reduction approach for single-bit compensation partial product but also enhances the efficiency and speed of the multiplier implementation. Extensive simulations, conducted using the TSMC 40-nm CMOS technology, have yielded compelling results. Compared to conventional radix-4 Booth multiplier implementations based on 3:2 compressors, the proposed design demonstrates a 26.61% improvement in speed, a 15.94% reduction in area, and a 9.83% decrease in power consumption. These enhancements collectively underscore the potential of the proposed 4:2 compressor to advance the state of the art in digital multiplier design, offering a more efficient and high-performance solution for a wide range of applications.</p>