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<p>The ternary logic-based system is superior to binary logic-based system because it requires less input lines and offers higher data density hence allows more information processing. In this paper, we propose various ternary circuits including, 1:3 ternary decoder, NANY gate and TSUM gate. All the circuits are implemented using Memristor &amp; 14&#xa0;nm FinFET hybrid technology. Compared to recent work with similar methodology the proposed designs are found notable for overall performance including PDP, noise margin and device count. The ternary decoder, NANY and TSUM gate have shown PDP improvement of 95%, 99.2% and 85% respectively and device count is improved by 16.6%, 88.4% and 6.6% respectively. Moreover, the proposed NANY and TSUM gate shows significant improvement in noise margin by 62% and 20% respectively. Additionally, the leakage power is reduced up to 90%. The proposed NANY compact structure (6 devices only) is the smallest – reported so far in open literature. All the proposed primitive circuits are then used as building blocks to design high performance THA (Ternary Half Adder) &amp; TFA (Ternary full adder). This THA consumes (12.19&#xa0;µW) around 36% less dynamic power and has reduced device count by approx. 5%. While the TFA design consumes 28.33&#xa0;µW, offering 10% less dynamic power with approximately 17% reduction in device requirement. To validate the practical feasibility of the design, the proposed TFA is implemented using CAD Electric VLSI tool and the required physical area is 24&#xa0;µm × 83&#xa0;µm.</p>

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Performance-Driven Area Efficient Ternary Adder Architecture Using Memristor and 14 nm FinFET Technology

  • 期刊论文

  • 发表日期：

    2026年2月9日

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  • Madhu Verma,
  • Preeti Verma,
  • Jyoteesh Malhotra

摘要

The ternary logic-based system is superior to binary logic-based system because it requires less input lines and offers higher data density hence allows more information processing. In this paper, we propose various ternary circuits including, 1:3 ternary decoder, NANY gate and TSUM gate. All the circuits are implemented using Memristor & 14 nm FinFET hybrid technology. Compared to recent work with similar methodology the proposed designs are found notable for overall performance including PDP, noise margin and device count. The ternary decoder, NANY and TSUM gate have shown PDP improvement of 95%, 99.2% and 85% respectively and device count is improved by 16.6%, 88.4% and 6.6% respectively. Moreover, the proposed NANY and TSUM gate shows significant improvement in noise margin by 62% and 20% respectively. Additionally, the leakage power is reduced up to 90%. The proposed NANY compact structure (6 devices only) is the smallest – reported so far in open literature. All the proposed primitive circuits are then used as building blocks to design high performance THA (Ternary Half Adder) & TFA (Ternary full adder). This THA consumes (12.19 µW) around 36% less dynamic power and has reduced device count by approx. 5%. While the TFA design consumes 28.33 µW, offering 10% less dynamic power with approximately 17% reduction in device requirement. To validate the practical feasibility of the design, the proposed TFA is implemented using CAD Electric VLSI tool and the required physical area is 24 µm × 83 µm.